Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Converting Bool to Unsigned generates broken VHDL #77

leonschoorl opened this issue Sep 9, 2015 · 0 comments


None yet
1 participant
Copy link

commented Sep 9, 2015

Converting Bool to Unsigned (through Bit) generates broken VHDL.
This seems like kind of the same problem as #33


topEntity :: Unsigned 1
topEntity = unpack (pack True)

Clash generates:

  topLet_o <= unsigned(("1"));

Which Xilinx ISE and ModelSim don't like, ISE compains with:
Expression in type conversion to unsigned has 6 possible definitions in this scope, for example, std_ulogic_vector and std_logic_vector.

It should probably generate:

  topLet_o <= unsigned(std_logic_vector'("1"));
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
You can’t perform that action at this time.