Converting Bool to Unsigned generates broken VHDL

[leonschoorl]

Converting Bool to Unsigned (through Bit) generates broken VHDL.
This seems like kind of the same problem as #33

Using:

topEntity :: Unsigned 1
topEntity = unpack (pack True)

Clash generates:

  topLet_o <= unsigned(("1"));

Which Xilinx ISE and ModelSim don't like, ISE compains with:
Expression in type conversion to unsigned has 6 possible definitions in this scope, for example, std_ulogic_vector and std_logic_vector.

It should probably generate:

  topLet_o <= unsigned(std_logic_vector'("1"));