icetime: No path found

[gojimmypi]

when generating an icetime rpt file like this:

icetime -d hx8k -P tq144 -p syn/myfile.pcf -mtr myfile.rpt myfile.asc

icetime returns an error: No path found!; The myfile.asc from nextpnr exists, and same error occurs regardless if myfile.rpt already exists or not.

// Reading input .pcf file..
// Reading input .asc file..
// Reading 8k chipdb file..
// Creating timing netlist..
// Timing estimate: 0.00 ns (inf MHz)
No path found!

The source code shows that message in double report(std::string n = std::string()), acting as if no rpt file string was specified, but there must have been as a the myfile.rpt is generated despite the errors.

In this a known problem? There does not appear to be an open issue - but the only other google search result for icetime "No path found!" was found on a bounty page here.

[daveshah1]

Is it possible that this is an empty design? That would be the normal cause of this message, and corresponding "infinite" maximum frequency.

Otherwise, can you post sufficient information to reproduce this message (asc, verilog and pcf).

[gojimmypi]

This all started with me learning FPGA programming and looking at an AD/DA converter, and specifically this project mentioned here as a passthru example to get started. (I have more details for the AD/DA board on my blog).

My nextpnr output is here. There are a lot of zeros, so perhaps indeed it is empty? I renamed everything to myfile to ensure the dashes in the filenames were not getting confused with commandline parameters.

If indeed this is due to an empty asc file - that would be a great feature to add to icetime say that. :)

The specific constraint file they are using is here with top.v, but copied here for this issue:

verilog:

/*
 * Copyright (c) 2018 Joel Holdsworth <joel@airwebreathe.org.uk>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived from
 *    this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

module top(clk_100mhz, adclk, addb, daclk, dadb);
parameter ClkFreq = 50000000; // Hz

input clk_100mhz;
output adclk;
input [7:0] addb;
output daclk;
output [7:0] dadb;

// Clock Generator
wire clk_50mhz;
wire pll_locked;

SB_PLL40_PAD #(
  .FEEDBACK_PATH("SIMPLE"),
  .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
  .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
  .PLLOUT_SELECT("GENCLK"),
  .FDA_FEEDBACK(4'b1111),
  .FDA_RELATIVE(4'b1111),
  .DIVR(4'b0000),
  .DIVF(7'b0000111),
  .DIVQ(3'b100),
  .FILTER_RANGE(3'b101)
) pll (
  .PACKAGEPIN(clk_100mhz),
  .PLLOUTGLOBAL(clk_50mhz),
  .LOCK(pll_locked),
  .BYPASS(1'b0),
  .RESETB(1'b1)
);

wire clk = clk_50mhz;

// Reset Generator
reg [3:0] resetn_gen = 0;
reg reset;

always @(posedge clk) begin
  reset <= !&resetn_gen;
  resetn_gen <= {resetn_gen, pll_locked};
end

endmodule

and pcf:

#
# Copyright (c) 2018 Joel Holdsworth <joel@airwebreathe.org.uk>
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
#    this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
#    notice, this list of conditions and the following disclaimer in the
#    documentation and/or other materials provided with the distribution.
# 3. Neither the name of copyright holder nor the names of its
#    contributors may be used to endorse or promote products derived from
#    this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#

set_io clk_100mhz R9

set_io adclk E6
set_io addb[0] D1
set_io addb[1] D2
set_io addb[2] C1
set_io addb[3] C2
set_io addb[4] B1
set_io addb[5] B2
set_io addb[6] A1
set_io addb[7] C5

set_io daclk H4
set_io dadb[0] H3
set_io dadb[1] J1
set_io dadb[2] J2
set_io dadb[3] K1
set_io dadb[4] L1
set_io dadb[5] H5
set_io dadb[6] M1
set_io dadb[7] M2

here's the modified Makefile I created (adapted from an example) to isolate the error:

PROJ = otl-modem
PIN_DEF = syn/otl-modem.pcf
DEVICE = hx8k

ARACHNE = arachne-pnr 
ARACHNE_ARGS = 
ICEPACK = icepack
ICETIME = icetime
ICEPROG = iceprog

src=

all: $(PROJ).bin

synthesize: otl-modem.bin

%.blif: syn/top.v $(src)
	yosys -p 'synth_ice40 -top top -blif $@' $<
	# yosys -q -p "synth_ice40 -blif otl-modem.blif" syn/top.v $(src)

%.asc: $(PIN_DEF) %.blif
	$(ARACHNE) $(ARACHNE_ARGS) -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) -o $@ -p $^

# otl-modem.asc: otl-modem.blif syn/otl-modem.pcf
	# arachne-pnr -d 8k -p syn/otl-modem.pcf $< -o $@
	# echo "---Running icetime!" $<
	# icetime -c 50 -p syn/otl-modem.pcf  -tm -d hx8k $@
	# icetime -d hx8k -c 50 otl-modem.asc
	# echo "---Done with icetime!"

%.rpt: %.asc
	$(ICETIME) -d $(DEVICE) -P tq144 -p syn/otl-modem.pcf -mtr $@ $<

%.bin: %.asc
	$(ICEPACK) $< $@
#otl-modem.bin: otl-modem.asc
#	echo "Running icepak!"
#	icepack $< $@

simulate-ft2232h_interface: ft2232h_interface.vcd
	gtkwave $< >/dev/null 2>/dev/null &

ft2232h_interface-sim: \
	sim/ft2232h_interface.v \
	src/ft2232h_interface.v
	iverilog -o $@ $^

%.vcd: %-sim
	cd $(dir $<); ./$(notdir $<)

clean:
	rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin

.SECONDARY:
.PHONY: all prog clean

.PHONY: \
  synthesize \
  simulate-ft2232h_interface \

[daveshah1]

This is indeed an empty design for the purposes of icetime (all it has is some disconnected input and output ports after dangling cells are swept away).

[daveshah1]

FYI, the "no path found" message was added to clear up this case in #45.

[gojimmypi]

Thank you for your help. I'm going to leave this issue open, with the suggestion that the No path found error (which sounds like a file system warning) be changed to the text noted in #45:

This design is empty. It contains no paths.

I created #205 for this.

[cliffordwolf]

Merged #205.