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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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# 12 MHz clock | ||
set_io clk 35 | ||
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# RS232 | ||
set_io ser_rx 6 | ||
set_io ser_tx 9 | ||
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# SPI Flash | ||
set_io flash_clk 15 | ||
set_io flash_csb 16 | ||
set_io flash_io0 14 | ||
set_io flash_io1 17 | ||
set_io flash_io2 12 | ||
set_io flash_io3 13 | ||
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# LEDs (PMOD 2) | ||
set_io led1 27 | ||
set_io led2 25 | ||
set_io led3 21 | ||
set_io led4 23 | ||
set_io led5 26 | ||
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# Onboard LEDs | ||
set_io ledr_n 11 | ||
set_io ledg_n 37 |
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/* | ||
* PicoSoC - A simple example SoC using PicoRV32 | ||
* | ||
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> | ||
* | ||
* Permission to use, copy, modify, and/or distribute this software for any | ||
* purpose with or without fee is hereby granted, provided that the above | ||
* copyright notice and this permission notice appear in all copies. | ||
* | ||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
* | ||
*/ | ||
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module icebreaker ( | ||
input clk, | ||
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output ser_tx, | ||
input ser_rx, | ||
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output led1, | ||
output led2, | ||
output led3, | ||
output led4, | ||
output led5, | ||
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output ledr_n, | ||
output ledg_n, | ||
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output flash_csb, | ||
output flash_clk, | ||
inout flash_io0, | ||
inout flash_io1, | ||
inout flash_io2, | ||
inout flash_io3 | ||
); | ||
reg [5:0] reset_cnt = 0; | ||
wire resetn = &reset_cnt; | ||
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always @(posedge clk) begin | ||
reset_cnt <= reset_cnt + !resetn; | ||
end | ||
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wire [7:0] leds; | ||
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assign led1 = leds[1]; | ||
assign led2 = leds[2]; | ||
assign led3 = leds[3]; | ||
assign led4 = leds[4]; | ||
assign led5 = leds[5]; | ||
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assign ledr_n = !leds[6]; | ||
assign ledg_n = !leds[7]; | ||
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wire flash_io0_oe, flash_io0_do, flash_io0_di; | ||
wire flash_io1_oe, flash_io1_do, flash_io1_di; | ||
wire flash_io2_oe, flash_io2_do, flash_io2_di; | ||
wire flash_io3_oe, flash_io3_do, flash_io3_di; | ||
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SB_IO #( | ||
.PIN_TYPE(6'b 1010_01), | ||
.PULLUP(1'b 0) | ||
) flash_io_buf [3:0] ( | ||
.PACKAGE_PIN({flash_io3, flash_io2, flash_io1, flash_io0}), | ||
.OUTPUT_ENABLE({flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}), | ||
.D_OUT_0({flash_io3_do, flash_io2_do, flash_io1_do, flash_io0_do}), | ||
.D_IN_0({flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di}) | ||
); | ||
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wire iomem_valid; | ||
reg iomem_ready; | ||
wire [3:0] iomem_wstrb; | ||
wire [31:0] iomem_addr; | ||
wire [31:0] iomem_wdata; | ||
reg [31:0] iomem_rdata; | ||
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reg [31:0] gpio; | ||
assign leds = gpio; | ||
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always @(posedge clk) begin | ||
if (!resetn) begin | ||
gpio <= 0; | ||
end else begin | ||
iomem_ready <= 0; | ||
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin | ||
iomem_ready <= 1; | ||
iomem_rdata <= gpio; | ||
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0]; | ||
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8]; | ||
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16]; | ||
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24]; | ||
end | ||
end | ||
end | ||
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picosoc #( | ||
.BARREL_SHIFTER(0), | ||
.ENABLE_MULDIV(0) | ||
) soc ( | ||
.clk (clk ), | ||
.resetn (resetn ), | ||
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.ser_tx (ser_tx ), | ||
.ser_rx (ser_rx ), | ||
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.flash_csb (flash_csb ), | ||
.flash_clk (flash_clk ), | ||
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.flash_io0_oe (flash_io0_oe), | ||
.flash_io1_oe (flash_io1_oe), | ||
.flash_io2_oe (flash_io2_oe), | ||
.flash_io3_oe (flash_io3_oe), | ||
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.flash_io0_do (flash_io0_do), | ||
.flash_io1_do (flash_io1_do), | ||
.flash_io2_do (flash_io2_do), | ||
.flash_io3_do (flash_io3_do), | ||
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.flash_io0_di (flash_io0_di), | ||
.flash_io1_di (flash_io1_di), | ||
.flash_io2_di (flash_io2_di), | ||
.flash_io3_di (flash_io3_di), | ||
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.irq_5 (1'b0 ), | ||
.irq_6 (1'b0 ), | ||
.irq_7 (1'b0 ), | ||
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.iomem_valid (iomem_valid ), | ||
.iomem_ready (iomem_ready ), | ||
.iomem_wstrb (iomem_wstrb ), | ||
.iomem_addr (iomem_addr ), | ||
.iomem_wdata (iomem_wdata ), | ||
.iomem_rdata (iomem_rdata ) | ||
); | ||
endmodule |
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/* | ||
* PicoSoC - A simple example SoC using PicoRV32 | ||
* | ||
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> | ||
* | ||
* Permission to use, copy, modify, and/or distribute this software for any | ||
* purpose with or without fee is hereby granted, provided that the above | ||
* copyright notice and this permission notice appear in all copies. | ||
* | ||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
* | ||
*/ | ||
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`timescale 1 ns / 1 ps | ||
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module testbench; | ||
reg clk; | ||
always #5 clk = (clk === 1'b0); | ||
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localparam ser_half_period = 53; | ||
event ser_sample; | ||
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initial begin | ||
$dumpfile("testbench.vcd"); | ||
$dumpvars(0, testbench); | ||
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repeat (6) begin | ||
repeat (50000) @(posedge clk); | ||
$display("+50000 cycles"); | ||
end | ||
$finish; | ||
end | ||
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integer cycle_cnt = 0; | ||
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always @(posedge clk) begin | ||
cycle_cnt <= cycle_cnt + 1; | ||
end | ||
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wire led1, led2, led3, led4, led5; | ||
wire ledr_n, ledg_n; | ||
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wire [6:0] leds = {!ledg_n, !ledr_n, led5, led4, led3, led2, led1}; | ||
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wire ser_rx; | ||
wire ser_tx; | ||
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wire flash_csb; | ||
wire flash_clk; | ||
wire flash_io0; | ||
wire flash_io1; | ||
wire flash_io2; | ||
wire flash_io3; | ||
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always @(leds) begin | ||
#1 $display("%b", leds); | ||
end | ||
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icebreaker uut ( | ||
.clk (clk ), | ||
.led1 (led1 ), | ||
.led2 (led2 ), | ||
.led3 (led3 ), | ||
.led4 (led4 ), | ||
.led5 (led5 ), | ||
.ledr_n (ledr_n ), | ||
.ledg_n (ledg_n ), | ||
.ser_rx (ser_rx ), | ||
.ser_tx (ser_tx ), | ||
.flash_csb(flash_csb), | ||
.flash_clk(flash_clk), | ||
.flash_io0(flash_io0), | ||
.flash_io1(flash_io1), | ||
.flash_io2(flash_io2), | ||
.flash_io3(flash_io3) | ||
); | ||
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spiflash spiflash ( | ||
.csb(flash_csb), | ||
.clk(flash_clk), | ||
.io0(flash_io0), | ||
.io1(flash_io1), | ||
.io2(flash_io2), | ||
.io3(flash_io3) | ||
); | ||
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reg [7:0] buffer; | ||
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always begin | ||
@(negedge ser_tx); | ||
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repeat (ser_half_period) @(posedge clk); | ||
-> ser_sample; // start bit | ||
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repeat (8) begin | ||
repeat (ser_half_period) @(posedge clk); | ||
repeat (ser_half_period) @(posedge clk); | ||
buffer = {ser_tx, buffer[7:1]}; | ||
-> ser_sample; // data bit | ||
end | ||
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repeat (ser_half_period) @(posedge clk); | ||
repeat (ser_half_period) @(posedge clk); | ||
-> ser_sample; // stop bit | ||
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if (buffer < 32 || buffer >= 127) | ||
$display("Serial data: %d", buffer); | ||
else | ||
$display("Serial data: '%c'", buffer); | ||
end | ||
endmodule |
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