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This is a repository containing the Verilog CPU Design files for the working processor I designed in Elec 5200. using the Verilog Hardware Description Language

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5200 CPU Design Project Part 5 Report.docx
5200 CPU Design Project Part 5 Report.docx
 
 
5200 CPU Design Project Part 6.pdf
5200 CPU Design Project Part 6.pdf
 
 
5200 cpu design project ISA Travis Keller - Sheet1.csv
5200 cpu design project ISA Travis Keller - Sheet1.csv
 
 
5200 cpu design project ISA Travis Keller - Sheet2.csv
5200 cpu design project ISA Travis Keller - Sheet2.csv
 
 
ALU1.v
ALU1.v
 
 
ALU2.v
ALU2.v
 
 
Adder.v
Adder.v
 
 
Control.v
Control.v
 
 
Data Memory.v
Data Memory.v
 
 
Mux1.v
Mux1.v
 
 
Mux2.v
Mux2.v
 
 
Mux3.v
Mux3.v
 
 
Mux4.v
Mux4.v
 
 
Mux5.v
Mux5.v
 
 
Program Counter.v
Program Counter.v
 
 
Program Memory.v
Program Memory.v
 
 
README.md
README.md
 
 
Register File.v
Register File.v
 
 
Rtype Logic Box.v
Rtype Logic Box.v
 
 
Top.v
Top.v
 
 
cpu design cleaned and submitted for part 5.zip
cpu design cleaned and submitted for part 5.zip
 
 
data_loader.txt
data_loader.txt
 
 
program_loader.txt.txt
program_loader.txt.txt
 
 

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This is a repository for the CPU I designed in ELEC 5200 Computer Architecture at Auurn Unversity in Fall 2018 using the Verilog HDL and Vivado Design Suite. I have also included project reports and the ISA explanation for each of the 14 instructions.

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This is a repository containing the Verilog CPU Design files for the working processor I designed in Elec 5200. using the Verilog Hardware Description Language

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