misc: Fix spelling issues

Misspellings were identified by:
  https://github.com/marketplace/actions/check-spelling

* Initial corrections based on forbidden patterns from the action
* Additional corrections by Google Chrome auto-suggest
* Some manual corrections
* Adding markdown bullets to readme credits section

Signed-off-by: Josh Soref <2119212+jsoref@users.noreply.github.com>

.taplo.toml

@@ -1,5 +1,5 @@
 include = ["**/Cargo.toml"]
 
 [formatting]
-reoder_arrays = true
+reorder_arrays = true
 reorder_keys = true

CONTRIBUTING.md

@@ -112,5 +112,5 @@ Fixes #88
 Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
 ```
 
-Then, after the corresponding PR is merged, Github will automatically close that issue when parsing the
+Then, after the corresponding PR is merged, GitHub will automatically close that issue when parsing the
 [commit message](https://help.github.com/articles/closing-issues-via-commit-messages/).

arch/src/aarch64/fdt.rs

@@ -525,7 +525,7 @@ fn create_memory_node(
                 let memory_region_size: u64 = memory_region.size() as u64;
                 mem_reg_prop.push(memory_region_start_addr);
                 mem_reg_prop.push(memory_region_size);
-                // Set the node address the first non-zero regison address
+                // Set the node address the first non-zero region address
                 if node_memory_addr == 0 {
                     node_memory_addr = memory_region_start_addr;
                 }
@@ -571,7 +571,7 @@ fn create_memory_node(
 
         if ram_regions.len() > 2 {
             panic!(
-                "There should be up to two non-continuous regions, devidided by the
+                "There should be up to two non-continuous regions, divided by the
                     gap at the end of 32bit address space."
             );
         }
@@ -896,7 +896,7 @@ fn create_pci_nodes(
     for pci_device_info_elem in pci_device_info.iter() {
         // EDK2 requires the PCIe high space above 4G address.
         // The actual space in CLH follows the RAM. If the RAM space is small, the PCIe high space
-        // could fall bellow 4G.
+        // could fall below 4G.
         // Here we cut off PCI device space below 8G in FDT to workaround the EDK2 check.
         // But the address written in ACPI is not impacted.
         let (pci_device_base_64bit, pci_device_size_64bit) =

arch/src/x86_64/mod.rs

@@ -577,7 +577,7 @@ impl CpuidFeatureEntry {
             if !entry_compatible {
                 error!(
                     "Detected incompatible CPUID entry: leaf={:#02x} (subleaf={:#02x}), register='{:?}', \
-                    compatilbe_check='{:?}', source VM feature='{:#04x}', destination VM feature'{:#04x}'.",
+                    compatible_check='{:?}', source VM feature='{:#04x}', destination VM feature'{:#04x}'.",
                     entry.function, entry.index, entry.feature_reg,
                     entry.compatible_check, src_vm_feature, dest_vm_feature
                     );

block/src/qcow/mod.rs

@@ -1200,7 +1200,7 @@ impl QcowFile {
     }
 
     // Allocate and initialize a new data cluster. Returns the offset of the
-    // cluster in to the file on success.
+    // cluster into the file on success.
     fn append_data_cluster(&mut self, initial_data: Option<Vec<u8>>) -> std::io::Result<u64> {
         let new_addr: u64 = self.get_new_cluster(initial_data)?;
         // The cluster refcount starts at one indicating it is used but doesn't need COW.

block/src/qcow/refcount.rs

@@ -28,7 +28,7 @@ pub enum Error {
     /// `NeedNewCluster` - Handle this error by allocating a cluster and calling the function again.
     #[error("New cluster needs to be allocated for refcounts")]
     NeedNewCluster,
-    /// `ReadingRefCounts` - Error reading the file in to the refcount cache.
+    /// `ReadingRefCounts` - Error reading the file into the refcount cache.
     #[error("Failed to read the file into the refcount cache: {0}")]
     ReadingRefCounts(io::Error),
 }

block/src/vhdx/vhdx_header.rs

@@ -127,7 +127,7 @@ pub struct Header {
 impl Header {
     /// Reads the Header structure from a reference VHDx file
     pub fn new(f: &mut File, start: u64) -> Result<Header> {
-        // Read the whole header in to a buffer. We will need it for
+        // Read the whole header into a buffer. We will need it for
         // calculating checksum.
         let mut buffer = [0; HEADER_SIZE as usize];
         f.seek(SeekFrom::Start(start))
@@ -470,7 +470,7 @@ impl VhdxHeader {
 pub fn calculate_checksum(buffer: &mut [u8], csum_offset: usize) -> Result<u32> {
     // Read the checksum into a mutable slice
     let csum_buf = &mut buffer[csum_offset..csum_offset + 4];
-    // Convert the checksum chunk in to a u32 integer
+    // Convert the checksum chunk into a u32 integer
     let orig_csum = LittleEndian::read_u32(csum_buf);
     // Zero the checksum in the buffer
     LittleEndian::write_u32(csum_buf, 0);

devices/src/tpm.rs

@@ -450,7 +450,7 @@ impl BusDevice for Tpm {
                         );
                     }
                     _ => {
-                        error!("Invalid value passed to CRTL_REQ register");
+                        error!("Invalid value passed to CTRL_REQ register");
                         return None;
                     }
                 },

docs/api.md

@@ -270,7 +270,7 @@ definition in XML format:
 ### Command Line Interface
 
 The Cloud Hypervisor Command Line Interface (CLI) can only be used for launching
-the Cloud Hypervisor binary, i.e. it can not be used for controlling the VMM or
+the Cloud Hypervisor binary, i.e. it cannot be used for controlling the VMM or
 the launched VM once they're up and running.
 
 If you want to inspect the VMM, or control the VM after launching Cloud

docs/custom-image.md

@@ -159,10 +159,10 @@ as we might need to update the direct kernel boot command line, replacing
 
 Update all references to the previous image name to the new one.
 
-## NVIDIA image for VFIO baremetal CI
+## NVIDIA image for VFIO bare-metal CI
 
 Here we are going to describe how to create a cloud image that contains the
-necessary NVIDIA drivers for our VFIO baremetal CI.
+necessary NVIDIA drivers for our VFIO bare-metal CI.
 
 ### Download base image
 

docs/fuzzing.md

@@ -2,7 +2,7 @@
 
 Cloud Hypervisor uses [cargo-fuzz](https://github.com/rust-fuzz/cargo-fuzz) for fuzzing individual components.
 
-The fuzzers are are in the `fuzz/fuzz_targets` directory
+The fuzzers are in the `fuzz/fuzz_targets` directory
 
 ## Preparation
 

docs/hotplug.md

@@ -53,7 +53,7 @@ On-line CPU(s) list:             0-7
 
 After a reboot the added CPUs will remain.
 
-Removing CPUs works similarly by reducing the number in the "desired_vcpus" field of the reisze API. The CPUs will be automatically offlined inside the guest so there is no need to run any commands inside the guest:
+Removing CPUs works similarly by reducing the number in the "desired_vcpus" field of the resize API. The CPUs will be automatically offlined inside the guest so there is no need to run any commands inside the guest:
 
 ```shell
 ./ch-remote --api-socket=/tmp/ch-socket resize --cpus 2

docs/iommu.md

@@ -39,7 +39,7 @@ Another reason for having a virtual IOMMU is to allow passing physical devices
 from the host through multiple layers of virtualization. Let's take as example
 a system with a physical IOMMU running a VM with a virtual IOMMU. The
 implementation of the virtual IOMMU is responsible for updating the physical
-DMA Remapping table (DMAR) everytime the DMA mapping changes. This must happen
+DMA Remapping table (DMAR) every time the DMA mapping changes. This must happen
 through the VFIO framework on the host as this is the only userspace interface
 to interact with a physical IOMMU.
 
@@ -124,7 +124,7 @@ On AArch64 architecture, the virtual IOMMU can still be used even if ACPI is not
 enabled. But the effect is different with what the aforementioned test showed.
 
 When ACPI is disabled, virtual IOMMU is supported through Flattened Device Tree
-(FDT). In this case, the guest kernel can not tell which device should be
+(FDT). In this case, the guest kernel cannot tell which device should be
 IOMMU-attached and which should not. No matter how many devices you attached to
 the virtual IOMMU by setting `iommu=on` option, all the devices on the PCI bus
 will be attached to the virtual IOMMU (except the IOMMU itself). Each of the

docs/memory.md

@@ -466,7 +466,7 @@ List of virtual CPUs attached to the guest NUMA node identified by the
 `guest_numa_id` option. This allows for describing a list of CPUs which
 must be seen by the guest as belonging to the NUMA node `guest_numa_id`.
 
-One can use this option for a fine grained description of the NUMA topology
+One can use this option for a fine-grained description of the NUMA topology
 regarding the CPUs associated with it, which might help the guest run more
 efficiently.
 
@@ -573,7 +573,7 @@ _Example_
 ### PCI bus
 
 Cloud Hypervisor supports guests with one or more PCI segments. The default PCI segment always
-has affinity to NUMA node 0. Be default, all other PCI segments have afffinity to NUMA node 0.
+has affinity to NUMA node 0. Be default, all other PCI segments have affinity to NUMA node 0.
 The user may configure the NUMA affinity for any additional PCI segments.
 
 _Example_

docs/releases.md

@@ -95,7 +95,7 @@ E - EOL
 
 ```
 
-### LTS Stablity Considerations
+### LTS Stability Considerations
 
 An LTS release is just a `MAJOR` release for which point releases are made for
 longer following the same rules for what can be backported to a `POINT` release.

docs/tracing.md

@@ -37,6 +37,6 @@ generating traces of the boot. These can be relocated for focus tracing on a
 narrow part of the code base.
 
 A `tracer::trace_point!()` macro is also provided for an instantaneous trace
-point however this is not in use in the code base currently nor is handled by
+point however this is neither in use in the code base currently nor is handled by
 the visualisation script due to the difficulty in representation in the SVG.
 

hypervisor/src/arch/x86/emulator/mod.rs

@@ -135,7 +135,7 @@ pub trait CpuStateManager: Clone {
                     .checked_add(segment_register.base)
                     .ok_or_else(|| {
                         PlatformError::InvalidAddress(anyhow!(
-                            "Logical address {:#x} can not be linearized with segment {:#x?}",
+                            "Logical address {:#x} cannot be linearized with segment {:#x?}",
                             logical_addr,
                             segment_register
                         ))
@@ -148,7 +148,7 @@ pub trait CpuStateManager: Clone {
                 // Must not write to a read-only segment.
                 if segment_type_ro(segment_type) && write {
                     return Err(PlatformError::InvalidAddress(anyhow!(
-                        "Can not write to a read-only segment"
+                        "Cannot write to a read-only segment"
                     )));
                 }
 

hypervisor/src/hypervisor.rs

@@ -166,7 +166,7 @@ pub trait Hypervisor: Send + Sync {
                 CpuVendor::AMD
             } else {
                 // Not known yet, the corresponding manufacturer manual should contain the
-                // necesssary info. See also https://wiki.osdev.org/CPUID#CPU_Vendor_ID_String
+                // necessary info. See also https://wiki.osdev.org/CPUID#CPU_Vendor_ID_String
                 CpuVendor::default()
             }
         }

hypervisor/src/kvm/aarch64/gic/redist_regs.rs

@@ -46,7 +46,7 @@ const KVM_ARM64_SYSREG_MPIDR_EL1: u64 = KVM_REG_ARM64
     | (((5_u64) << KVM_REG_ARM64_SYSREG_OP2_SHIFT) & KVM_REG_ARM64_SYSREG_OP2_MASK as u64);
 
 /// This is how we represent the registers of a distributor.
-/// It is relrvant their offset from the base address of the
+/// It is relevant their offset from the base address of the
 /// distributor.
 /// Each register has a different number
 /// of bits_per_irq and is therefore variable length.

hypervisor/src/kvm/mod.rs

@@ -535,9 +535,9 @@ impl vm::Vm for KvmVm {
 
                 if self.check_extension(crate::kvm::Cap::MsiDevid) {
                     // On AArch64, there is limitation on the range of the 'devid',
-                    // it can not be greater than 65536 (the max of u16).
+                    // it cannot be greater than 65536 (the max of u16).
                     //
-                    // BDF can not be used directly, because 'segment' is in high
+                    // BDF cannot be used directly, because 'segment' is in high
                     // 16 bits. The layout of the u32 BDF is:
                     // |---- 16 bits ----|-- 8 bits --|-- 5 bits --|-- 3 bits --|
                     // |      segment    |     bus    |   device   |  function  |
@@ -1505,7 +1505,7 @@ impl cpu::Vcpu for KvmVcpu {
 
     #[cfg(target_arch = "x86_64")]
     ///
-    /// Set the floating point state (FPU) of a vCPU using the `KVM_SET_FPU` ioct.
+    /// Set the floating point state (FPU) of a vCPU using the `KVM_SET_FPU` ioctl.
     ///
     fn set_fpu(&self, fpu: &FpuState) -> cpu::Result<()> {
         let fpu: kvm_bindings::kvm_fpu = (*fpu).clone().into();
@@ -1986,7 +1986,7 @@ impl cpu::Vcpu for KvmVcpu {
     /// SREGS saves/restores a pending interrupt, similar to what
     /// VCPU_EVENTS also does.
     ///
-    /// GET_MSRS requires a pre-populated data structure to do something
+    /// GET_MSRS requires a prepopulated data structure to do something
     /// meaningful. For SET_MSRS it will then contain good data.
     ///
     /// # Example

hypervisor/src/mshv/mod.rs

@@ -1329,7 +1329,7 @@ impl cpu::Vcpu for MshvVcpu {
         self.set_fpu(&state.fpu)?;
         self.set_xcrs(&state.xcrs)?;
         // These registers are global and needed to be set only for first VCPU
-        // as Microsoft Hypervisor allows setting this regsier for only one VCPU
+        // as Microsoft Hypervisor allows setting this register for only one VCPU
         if self.vp_index == 0 {
             self.fd
                 .set_misc_regs(&state.misc)

hypervisor/src/vm.rs

@@ -190,7 +190,7 @@ pub enum HypervisorVmError {
     /// Assert virtual interrupt error
     ///
     #[error("Failed to assert virtual Interrupt: {0}")]
-    AsserttVirtualInterrupt(#[source] anyhow::Error),
+    AssertVirtualInterrupt(#[source] anyhow::Error),
 
     #[cfg(feature = "sev_snp")]
     ///

net_util/src/queue_pair.rs

@@ -418,7 +418,7 @@ impl NetQueuePair {
             .map_or(false, |r| r.is_blocked());
 
         // Stop listening on the `RX_TAP_EVENT` when:
-        // 1) there is no available describles, or
+        // 1) there is no available describes, or
         // 2) the RX rate limit is reached.
         if self.rx_tap_listening && (!self.rx_desc_avail || rate_limit_reached) {
             unregister_listener(

pci/src/configuration.rs

@@ -291,7 +291,7 @@ pub enum PciExpressCapabilityId {
     VfResizeableBar = 0x0024,
     DataLinkFeature = 0x0025,
     PhysicalLayerSixteenGts = 0x0026,
-    LaneMargeningAtTheReceiver = 0x0027,
+    LaneMarginingAtTheReceiver = 0x0027,
     HierarchyId = 0x0028,
     NativePcieEnclosureManagement = 0x0029,
     PhysicalLayerThirtyTwoGts = 0x002a,
@@ -345,7 +345,7 @@ impl From<u16> for PciExpressCapabilityId {
             0x0024 => PciExpressCapabilityId::VfResizeableBar,
             0x0025 => PciExpressCapabilityId::DataLinkFeature,
             0x0026 => PciExpressCapabilityId::PhysicalLayerSixteenGts,
-            0x0027 => PciExpressCapabilityId::LaneMargeningAtTheReceiver,
+            0x0027 => PciExpressCapabilityId::LaneMarginingAtTheReceiver,
             0x0028 => PciExpressCapabilityId::HierarchyId,
             0x0029 => PciExpressCapabilityId::NativePcieEnclosureManagement,
             0x002a => PciExpressCapabilityId::PhysicalLayerThirtyTwoGts,

pci/src/device.rs

@@ -79,7 +79,7 @@ pub trait PciDevice: BusDevice {
 
     /// Sets a register in the configuration space.
     /// * `reg_idx` - The index of the config register to modify.
-    /// * `offset` - Offset in to the register.
+    /// * `offset` - Offset into the register.
     fn write_config_register(
         &mut self,
         reg_idx: usize,
@@ -97,11 +97,11 @@ pub trait PciDevice: BusDevice {
     ) -> Option<BarReprogrammingParams> {
         None
     }
-    /// Reads from a BAR region mapped in to the device.
+    /// Reads from a BAR region mapped into the device.
     /// * `addr` - The guest address inside the BAR.
     /// * `data` - Filled with the data from `addr`.
     fn read_bar(&mut self, _base: u64, _offset: u64, _data: &mut [u8]) {}
-    /// Writes to a BAR region mapped in to the device.
+    /// Writes to a BAR region mapped into the device.
     /// * `addr` - The guest address inside the BAR.
     /// * `data` - The data to write.
     fn write_bar(&mut self, _base: u64, _offset: u64, _data: &[u8]) -> Option<Arc<Barrier>> {

performance-metrics/src/performance_tests.rs

@@ -34,7 +34,7 @@ impl From<InfraError> for Error {
 const BLK_IO_TEST_IMG: &str = "/var/tmp/ch-blk-io-test.img";
 
 pub fn init_tests() {
-    // The test image can not be created on tmpfs (e.g. /tmp) filesystem,
+    // The test image cannot be created on tmpfs (e.g. /tmp) filesystem,
     // as tmpfs does not support O_DIRECT
     assert!(exec_host_command_output(&format!(
         "dd if=/dev/zero of={BLK_IO_TEST_IMG} bs=1M count=4096"
@@ -199,7 +199,7 @@ fn parse_boot_time_output(output: &[u8]) -> Result<f64, Error> {
             );
             assert!(
                 t[7].eq("seconds"),
-                "Expecting 'seconds' as the the last word of the 'Debug I/O port' output"
+                "Expecting 'seconds' as the last word of the 'Debug I/O port' output"
             );
 
             t[6].parse::<f64>().unwrap()
@@ -226,7 +226,7 @@ fn parse_boot_time_output(output: &[u8]) -> Result<f64, Error> {
             );
             assert!(
                 t[7].eq("seconds"),
-                "Expecting 'seconds' as the the last word of the 'Debug I/O port' output"
+                "Expecting 'seconds' as the last word of the 'Debug I/O port' output"
             );
 
             t[6].parse::<f64>().unwrap()