Implement GICv3 #1290
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wkozaczuk
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This patch implements GICv3 driver and thus allows OSv to run on modern SBCs (Single Board Computers) like Radxa's Rock 5B. It is also a prerequisite to support AWS Graviton. The code in gic-v3.** is somewhat based on the implementation of GICv3 in the Unikraft project (see https://github.com/unikraft/unikraft/blob/staging/drivers/ukintctlr/gic/gic-v3.*). It also re-uses elements from the abstract class gic-driver. Please note this implementation does not support MSI-X and LPIs (arm version of Message Signalled Interrupts). The code to initialize GICv3 is logically similar to GICv2 in that it needs to initialize so called distributor interface on boot cpu (see gic_v3_driver::init_dist()). And then it needs to call gic_v3_driver::init_redist(int smp_idx) in order to initialize so called redistributor interface specific to each cpu (kind of equivalent to cpu interface (cpuif) in GICv2). We also implement other key methods - mask_irq(), unmask_irq(), set_irq_type(), send_sgi(), ack_irq() and end_irq() - in a way specific to GICv3. Finally, the run.py has been modified to pass "gic-version=max" to make QEMU automatically expose the highest version of the GIC supported on given hardware platform. For more information about GICv3 look at this official ARM documentation: - GICv3 and GICv4 Software Overview: https://documentation-service.arm.com/static/5f1068720daa596235e7f6ef - Arm® Generic Interrupt Controller Architecture Specification (GIC architecture version 3 and version 4) - https://documentation-service.arm.com/static/601412d54ccc190e5e681269 Fixes cloudius-systems#1290 Signed-off-by: Waldemar Kozaczuk <jwkozaczuk@gmail.com>
This was referenced Jan 9, 2024
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wkozaczuk
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Jan 11, 2024
This patch implements GICv3 driver and thus allows OSv to run on modern SBCs (Single Board Computers) like Radxa's Rock 5B. It is also a prerequisite to support AWS Graviton. The code in gic-v3.** is somewhat based on the implementation of GICv3 in the Unikraft project (see https://github.com/unikraft/unikraft/blob/staging/drivers/ukintctlr/gic/gic-v3.*). It also re-uses elements from the abstract class gic-driver. Please note this implementation does not support MSI-X and LPIs (arm version of Message Signalled Interrupts). The code to initialize GICv3 is logically similar to GICv2 in that it needs to initialize so called distributor interface on boot cpu (see gic_v3_driver::init_dist()). And then it needs to call gic_v3_driver::init_redist(int smp_idx) in order to initialize so called redistributor interface specific to each cpu (kind of equivalent to cpu interface (cpuif) in GICv2). We also implement other key methods - mask_irq(), unmask_irq(), set_irq_type(), send_sgi(), ack_irq() and end_irq() - in a way specific to GICv3. Finally, the run.py has been modified to pass "gic-version=max" to make QEMU automatically expose the highest version of the GIC supported on given hardware platform. For more information about GICv3 look at this official ARM documentation: - GICv3 and GICv4 Software Overview: https://documentation-service.arm.com/static/5f1068720daa596235e7f6ef - Arm® Generic Interrupt Controller Architecture Specification (GIC architecture version 3 and version 4) - https://documentation-service.arm.com/static/601412d54ccc190e5e681269 Fixes #1290 Signed-off-by: Waldemar Kozaczuk <jwkozaczuk@gmail.com>
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At this moment our aarch64 port only supports the GICv2 interrupt controller. To make OSv run on modern arm devices, we need GICv3 support.
Please look at https://developer.arm.com/documentation/198123/0302/What-is-a-Generic-Interrupt-Controller- for more details.
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