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Simulate all ALCTs and CLCTs in the CSC trigger #29562
Simulate all ALCTs and CLCTs in the CSC trigger #29562
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The code-checks are being triggered in jenkins. |
+code-checks Logs: https://cmssdt.cern.ch/SDT/code-checks/cms-sw-PR-29562/14861
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A new Pull Request was created by @dildick (Sven Dildick) for master. It involves the following packages: L1Trigger/CSCCommonTrigger @cmsbuild, @rekovic, @benkrikler can you please review it and eventually sign? Thanks. cms-bot commands are listed here |
please test |
The tests are being triggered in jenkins. |
+1 |
Comparison job queued. |
Comparison is ready Comparison Summary:
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please test |
The tests are being triggered in jenkins. |
+1 |
Comparison job queued. |
Comparison is ready Comparison Summary:
|
Do you have any comments? @rekovic |
+1 |
This pull request is fully signed and it will be integrated in one of the next master IBs (tests are also fine). This pull request will now be reviewed by the release team before it's merged. @silviodonato, @dpiparo (and backports should be raised in the release meeting by the corresponding L2) |
+1 |
…100-revert-29562 Revert #29562 and use only low-quality ALCTs in ME2/1
…100-revert-29562 Revert #29562 and use only low-quality ALCTs in ME2/1
PR description:
The CSC trigger, more specific the ALCT and CLCT processors, consider all possible patterns for each wire-group and half-strip. However, this is in fact never done in the simulation. This pull request addresses that for the CLCT processor. In another PR, I'll do the same for the ALCT processor. Note that the correlation of ALCT and CLCT still only considers the best/second best of ALCT and CLCT.
Edit: I added an updated for the ALCT processor, simulating all ALCTs.
PR validation:
I made a few validation plots (see below) by re-emulating the ALCT/CLCT and LCT on 25000 events in the file block
/ZeroBias/Run2018D-v1/RAW#5dd68d0d-5a62-4bfe-9065-cc0cd92e3f3e
(/store/data/Run2018D/ZeroBias/RAW/v1/000/324/022/00000/
).Plots look good. You will notice slightly bigger differences from the positive endcap ("pAll"). This is because we were testing newer firmware during the 2018D period on a few ME+1/1 chambers.
if this PR is a backport please specify the original PR and why you need to backport that PR:
N/A
@tahuang1991