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HcalDQM: Revert timing bit to old default, backport of #39058 #39057

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Aug 23, 2022
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4 changes: 3 additions & 1 deletion DQM/HcalTasks/plugins/TPTask.cc
Original file line number Diff line number Diff line change
Expand Up @@ -1130,7 +1130,9 @@ TPTask::TPTask(edm::ParameterSet const& ps)
HcalElectronicsId const& eid(rawid);

const bool HetAgreement = sentTp.SOI_compressedEt() == recdTp.SOI_compressedEt();
const bool Hfb1Agreement = sentTp.SOI_fineGrain() == recdTp.SOI_fineGrain();
const bool Hfb1Agreement =
(abs(ieta) < 29) ? true
: (recdTp.SOI_compressedEt() == 0 || (sentTp.SOI_fineGrain() == recdTp.SOI_fineGrain()));
// Ignore minBias (FB2) bit if we receieve 0 ET, which means it is likely zero-suppressed on HCal readout side
const bool Hfb2Agreement =
(abs(ieta) < 29) ? true
Expand Down