Merge pull request #13 from cnpem-sei/PR-protect-spurious-sync-pulses

Protection against high frequency synchronization pulses

.launches/C28_V2.1.launch

@@ -30,8 +30,8 @@
 <stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\Users\allef.silva\lnls-elp\C28\targetConfigs\F28M36_TI_XDS100v2.ccxml.Texas Instruments XDS100v2 USB Debug Probe/C28xx_0" value="C:/Users\gabriel.brunheira\lnls-elp\C28\FLASH_UDC_V2_1\C28_V2.1.out"/>
 <stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\Users\allef.silva\lnls-elp\C28\targetConfigs\F28M36_TI_XDS110.ccxml.Texas Instruments XDS110 USB Debug Probe_0/C28xx_0" value="C:/Users\allef.silva\lnls-elp\C28\FLASH_UDC_V2_1\C28_V2.1.out"/>
 <stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\Users\allef.silva\lnls-elp\C28\targetConfigs\F28M36_TI_XDS110.ccxml.Texas Instruments XDS110 USB Debug Probe_0/Cortex_M3_0" value="C:/Users\allef.silva\lnls-elp\ARM\FLASH_UDC_V2_1\M3_V2.0.out"/>
-<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.F28M36_TI_XDS100v2.ccxml.Texas Instruments XDS100v2 USB Debug Probe/C28xx_0" value="C:\Users\gabriel.brunheira\lnls-elp\c28\FLASH_UDC_V2_1\C28_V2.1.out"/>
-<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.F28M36_TI_XDS100v2.ccxml.Texas Instruments XDS100v2 USB Debug Probe/Cortex_M3_0" value="C:\Users\gabriel.brunheira\lnls-elp\ARM\FLASH_UDC_V2_1\M3_V2.0.out"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.F28M36_TI_XDS100v2.ccxml.Texas Instruments XDS100v2 USB Debug Probe/C28xx_0" value="C:\Users\gabriel.brunheira\cnpem-sei\udc-dsp-fw\FLASH_UDC_V2_1\C28_V2.1.out"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.F28M36_TI_XDS100v2.ccxml.Texas Instruments XDS100v2 USB Debug Probe/Cortex_M3_0" value="C:\Users\gabriel.brunheira\cnpem-sei\udc-arm-fw\FLASH_UDC_V2_1\M3_V2.0.out"/>
 <stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.F28M36_TI_XDS110.ccxml.Texas Instruments XDS110 USB Debug Probe_0/C28xx_0" value="C:\Users\rogerio.marcondeli\lnls-elp\C28\FLASH_UDC_V2_1\C28_V2.1.out"/>
 <stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.F28M36_TI_XDS110.ccxml.Texas Instruments XDS110 USB Debug Probe_0/Cortex_M3_0" value="C:/Users\gabriel.brunheira\lnls-elp\ARM\FLASH_UDC_V2_1\M3_V2.0.out"/>
 <mapAttribute key="com.ti.ccstudio.debug.ui.displayFormats">

elp_libs/boards/version.c

@@ -21,4 +21,4 @@
 
 #include "version.h"
 
-const char * udc_c28_version = "V0.43 2021-12-02";
+const char * udc_c28_version = "V0.44 2022-06-30";

elp_libs/ipc/ipc.c

@@ -35,6 +35,8 @@ volatile float g_buf_samples_ctom[SIZE_BUF_SAMPLES_CTOM];
 volatile ipc_ctom_t g_ipc_ctom;
 volatile ipc_mtoc_t g_ipc_mtoc;
 
+volatile uint32_t counter_sync_period = MIN_NUM_ISR_CONTROLLER_SYNC;
+
 #pragma CODE_SECTION(isr_ipc_sync_pulse,"ramfuncs");
 
 /**
@@ -66,6 +68,7 @@ void init_ipc(void)
     g_ipc_ctom.error_mtoc = No_Error_MtoC;
     g_ipc_ctom.counter_set_slowref =  0;
     g_ipc_ctom.counter_sync_pulse =  0;
+    g_ipc_ctom.period_sync_pulse =  0;
 
     EALLOW;
 
@@ -78,9 +81,6 @@ void init_ipc(void)
     *   - Qualification is asynchronous
     *   - Enable XINT2
     *   - Map XINT2 ISR
-    *
-    *  TODO: choose between XINT2 or XINT3
-    *
     */
     if(UDC_V2_0)
     {
@@ -89,7 +89,6 @@ void init_ipc(void)
         GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 1;
 
         GpioTripRegs.GPTRIP5SEL.bit.GPTRIP5SEL = 32;
-        /*GpioTripRegs.GPTRIP6SEL.bit.GPTRIP6SEL = 32;*/
     }
 
     else if(UDC_V2_1)
@@ -106,13 +105,10 @@ void init_ipc(void)
          * TODO: improve GPIO selection
          */
         GpioTripRegs.GPTRIP5SEL.bit.GPTRIP5SEL = 55;//38;
-        /*GpioTripRegs.GPTRIP6SEL.bit.GPTRIP6SEL = 38;*/
     }
 
     XIntruptRegs.XINT2CR.bit.ENABLE = 1;
     XIntruptRegs.XINT2CR.bit.POLARITY = 0;
-    /*XIntruptRegs.XINT3CR.bit.ENABLE = 0;
-    XIntruptRegs.XINT3CR.bit.POLARITY = 0;*/
 
     /**
      * TODO: create enable and disable EPWMSYNCO functions on pwm module
@@ -126,14 +122,16 @@ void init_ipc(void)
     PieVectTable.MTOCIPC_INT1 = &isr_ipc_lowpriority_msg;
     PieVectTable.MTOCIPC_INT2 = &isr_ipc_sync_pulse;
     PieVectTable.XINT2        = &isr_ipc_sync_pulse;
-    //PieVectTable.XINT3      = &isr_ipc_sync_pulse;
     PieVectTable.MTOCIPC_INT3 = g_ipc_ctom.ps_module[0].isr_hard_interlock;
     PieVectTable.MTOCIPC_INT4 = g_ipc_ctom.ps_module[0].isr_soft_interlock;
 
     /* Enable interrupts */
 
-    PieCtrlRegs.PIEIER1.bit.INTx5  = 1;                 //    XINT2
-    //PieCtrlRegs.PIEIER12.bit.INTx1 = 1;               //    XINT3
+    /**
+     * XINT2 is now only enabled by isr_controller to keep one ISR for sync
+     * pulses for each controller period
+     * */
+    //PieCtrlRegs.PIEIER1.bit.INTx5  = 1;                 // XINT2
 
     PieCtrlRegs.PIEIER11.bit.INTx1 = 1;                 // MTOCIPCINT1
     PieCtrlRegs.PIEIER11.bit.INTx2 = 1;                 // MTOCIPCINT2
@@ -320,27 +318,12 @@ interrupt void isr_ipc_lowpriority_msg(void)
             case Enable_Scope:
             {
                 enable_scope(&SCOPE_CTOM[msg_id]);
-                //enable_buffer(&g_ipc_ctom.buf_samples[msg_id]);
-                /*enable_buffer(&g_ipc_ctom.buf_samples[0]);
-                enable_buffer(&g_ipc_ctom.buf_samples[1]);
-                enable_buffer(&g_ipc_ctom.buf_samples[2]);
-                enable_buffer(&g_ipc_ctom.buf_samples[3]);*/
                 break;
             }
 
             case Disable_Scope:
             {
-                /**
-                 * TODO: It sets as Postmortem to wait buffer complete. Maybe
-                 * it's better to create a postmortem BSMP function
-                 */
                 disable_scope(&SCOPE_CTOM[msg_id]);
-                //postmortem_buffer(&g_ipc_ctom.buf_samples[msg_id]);
-                /*postmortem_buffer(&g_ipc_ctom.buf_samples[0]);
-                postmortem_buffer(&g_ipc_ctom.buf_samples[1]);
-                postmortem_buffer(&g_ipc_ctom.buf_samples[2]);
-                postmortem_buffer(&g_ipc_ctom.buf_samples[3]);*/
-                //disable_buffer(&g_ipc_ctom.buf_samples[msg_id]);
                 break;
             }
 
@@ -498,7 +481,8 @@ interrupt void isr_ipc_sync_pulse(void)
 {
     uint16_t i;
 
-    SET_DEBUG_GPIO1;
+    SET_DEBUG_GPIO0;
+    //SET_DEBUG_GPIO1;
 
     for(i = 0; i < NUM_MAX_PS_MODULES; i++)
     {
@@ -537,14 +521,6 @@ interrupt void isr_ipc_sync_pulse(void)
 
     g_ipc_ctom.counter_sync_pulse++;
 
-    /*if(g_ipc_ctom.buf_samples[0].status == Idle)
-    {
-        g_ipc_ctom.buf_samples[0].status = Postmortem;
-        g_ipc_ctom.buf_samples[1].status = Postmortem;
-        g_ipc_ctom.buf_samples[2].status = Postmortem;
-        g_ipc_ctom.buf_samples[3].status = Postmortem;
-    }*/
-
     if(SCOPE_CTOM[0].buffer.status == Idle)
     {
         SCOPE_CTOM[0].buffer.status = Postmortem;
@@ -553,9 +529,39 @@ interrupt void isr_ipc_sync_pulse(void)
         SCOPE_CTOM[3].buffer.status = Postmortem;
     }
 
-    CtoMIpcRegs.MTOCIPCACK.all = SYNC_PULSE;
+    /**
+     * Safe procedure to disable the XINT2 PIEIER bit and preserve associated
+     * PIEIFR flags, as described in section 1.5.4.3.2 from F28M36 Technical
+     * Reference Manual (SPRUHE8E)
+     *
+     * TODO: check whether DINT and EINT are really necessary, since this
+     * procedure is executed inside a ISR.
+     */
+
+    /// 1) Disable global interrupts
+    DINT;
+
+    /// 2) Clear PIEIER bit to disable XINT2 (external interrupt 2) interrupt
+    PieCtrlRegs.PIEIER1.bit.INTx5 = 0;
+
+    /// 3) Wait 5 clock cycles
+    __asm(" NOP");
+    __asm(" NOP");
+    __asm(" NOP");
+    __asm(" NOP");
+    __asm(" NOP");
+
+    // 4) Clear CPU IFR bit for XINT2 interrupt group
+    IFR &= ~M_INT1;
+
+    /// 5) Clear PIEACK bit from XINT2 interrupt group.
     PieCtrlRegs.PIEACK.all |= M_INT1;
-    PieCtrlRegs.PIEACK.all |= M_INT11;
+    PieCtrlRegs.PIEACK.all |= M_INT11;          /// Here we also clear
+    CtoMIpcRegs.MTOCIPCACK.all = SYNC_PULSE;    /// MTOCIPCINT2 ACK bits
 
+    CLEAR_DEBUG_GPIO0;
     //CLEAR_DEBUG_GPIO1;
+
+    /// 6) Enable global interrupts
+    EINT;
 }

elp_libs/ipc/ipc.h

@@ -33,6 +33,12 @@
 #include "parameters/parameters.h"
 #include "scope/scope.h"
 
+/**
+ * Synchronization defines
+ */
+#define MIN_NUM_ISR_CONTROLLER_SYNC     1000
+#define MAX_NUM_ISR_CONTROLLER_SYNC     4294967295  // 0xFFFFFFFF
+
 /**
  * Shared resources defines
  */
@@ -129,6 +135,7 @@ typedef struct
     error_mtoc_t    error_mtoc;
     uint32_t        counter_set_slowref;
     uint32_t        counter_sync_pulse;
+    uint32_t        period_sync_pulse;
     ps_module_t     ps_module[NUM_MAX_PS_MODULES];
     siggen_t        siggen[NUM_MAX_PS_MODULES];
     wfmref_t        wfmref[NUM_MAX_PS_MODULES];
@@ -162,6 +169,8 @@ extern volatile float g_buf_samples_mtoc[SIZE_BUF_SAMPLES_MTOC];
 extern volatile ipc_ctom_t g_ipc_ctom;
 extern volatile ipc_mtoc_t g_ipc_mtoc;
 
+extern volatile uint32_t counter_sync_period;
+
 extern void init_ipc(void);
 extern void send_ipc_msg(uint16_t msg_id, uint32_t msg);
 extern void send_ipc_lowpriority_msg(uint16_t msg_id,

elp_libs/ps_modules/fac_2p4s_acdc.c

@@ -501,7 +501,7 @@ static interrupt void isr_controller(void)
     static float temp[4];
     static uint16_t i;
 
-    SET_DEBUG_GPIO0;
+    //SET_DEBUG_GPIO0;
     SET_DEBUG_GPIO1;
 
     temp[0] = 0.0;

elp_libs/ps_modules/fac_2p4s_dcdc.c

@@ -258,6 +258,11 @@ typedef enum
     Complementary_PS_Itlk
 } soft_interlocks_t;
 
+typedef enum
+{
+    High_Sync_Input_Frequency = 0x00000001
+} alarms_t;
+
 #define NUM_HARD_INTERLOCKS     IIB_Mod_8_Itlk + 1
 #define NUM_SOFT_INTERLOCKS     Complementary_PS_Itlk + 1
 
@@ -789,7 +794,18 @@ static interrupt void isr_init_controller(void)
     PWM_MODULATOR_Q2_MOD_3_7->ETSEL.bit.INTSEL = ET_CTR_ZERO;
     PWM_MODULATOR_Q2_MOD_3_7->ETCLR.bit.INT = 1;
 
+    /**
+     *  Enable XINT2 (external interrupt 2) interrupt used for sync pulses for
+     *  the first time
+     *
+     *  TODO: include here mechanism described in section 1.5.4.3 from F28M36
+     *  Technical Reference Manual (SPRUHE8E) to clear flag before enabling, to
+     *  avoid false alarms that may occur when sync pulses are received during
+     *  firmware initialization.
+     */
+    PieCtrlRegs.PIEIER1.bit.INTx5 = 1;
 
+    /// Clear interrupt flag for PWM interrupts group
     PieCtrlRegs.PIEACK.all |= M_INT3;
 }
 
@@ -802,7 +818,7 @@ static interrupt void isr_controller(void)
     static uint16_t i;
 
     //CLEAR_DEBUG_GPIO1;
-    SET_DEBUG_GPIO0;
+    //SET_DEBUG_GPIO0;
     SET_DEBUG_GPIO1;
 
     temp[0] = 0.0;
@@ -963,11 +979,41 @@ static interrupt void isr_controller(void)
 
     SET_INTERLOCKS_TIMEBASE_FLAG(0);
 
+    /**
+     * Re-enable external interrupt 2 (XINT2) interrupts to allow sync pulses to
+     * be handled once per isr_controller
+     */
+    if(PieCtrlRegs.PIEIER1.bit.INTx5 == 0)
+    {
+        /// Set alarm if counter is below limit when receiving new sync pulse
+        if(counter_sync_period < MIN_NUM_ISR_CONTROLLER_SYNC)
+        {
+            g_ipc_ctom.ps_module[0].ps_alarms = High_Sync_Input_Frequency;
+        }
+
+        /// Store counter value on BSMP variable
+        g_ipc_ctom.period_sync_pulse = counter_sync_period;
+        counter_sync_period = 0;
+    }
+
+    counter_sync_period++;
+
+    /**
+     * Reset counter to threshold to avoid false alarms during its overflow
+     */
+    if(counter_sync_period == MAX_NUM_ISR_CONTROLLER_SYNC)
+    {
+        counter_sync_period = MIN_NUM_ISR_CONTROLLER_SYNC;
+    }
+
+    /// Re-enable XINT2 (external interrupt 2) interrupt used for sync pulses
+    PieCtrlRegs.PIEIER1.bit.INTx5 = 1;
+
+    /// Clear interrupt flags for PWM interrupts
     PWM_MODULATOR_Q1_MOD_1_5->ETCLR.bit.INT = 1;
     PWM_MODULATOR_Q2_MOD_1_5->ETCLR.bit.INT = 1;
     PWM_MODULATOR_Q1_MOD_3_7->ETCLR.bit.INT = 1;
     PWM_MODULATOR_Q2_MOD_3_7->ETCLR.bit.INT = 1;
-
     PieCtrlRegs.PIEACK.all |= M_INT3;
 
     //CLEAR_DEBUG_GPIO0;
@@ -1082,6 +1128,7 @@ static void reset_interlocks(uint16_t dummy)
 {
     g_ipc_ctom.ps_module[0].ps_hard_interlock = 0;
     g_ipc_ctom.ps_module[0].ps_soft_interlock = 0;
+    g_ipc_ctom.ps_module[0].ps_alarms = 0;
 
     if(g_ipc_ctom.ps_module[0].ps_status.bit.state < Initializing)
     {

elp_libs/ps_modules/fac_2p_acdc_imas.c

@@ -551,7 +551,7 @@ static interrupt void isr_controller(void)
     static float temp[4];
     static uint16_t i;
 
-    SET_DEBUG_GPIO0;
+    //SET_DEBUG_GPIO0;
     SET_DEBUG_GPIO1;
 
     temp[0] = 0.0;

elp_libs/ps_modules/fac_2p_dcdc_imas.c

@@ -704,7 +704,7 @@ static interrupt void isr_controller(void)
     static uint16_t i;
 
     //CLEAR_DEBUG_GPIO1;
-    SET_DEBUG_GPIO0;
+    //SET_DEBUG_GPIO0;
     SET_DEBUG_GPIO1;
 
     temp[0] = 0.0;

elp_libs/ps_modules/fac_2s_acdc.c

@@ -501,7 +501,7 @@ static interrupt void isr_controller(void)
     static float temp[4];
     static uint16_t i;
 
-    SET_DEBUG_GPIO0;
+    //SET_DEBUG_GPIO0;
     SET_DEBUG_GPIO1;
 
     temp[0] = 0.0;