start bi-weekly-rpt-2018-05-11.

[xfguo]

News

• SiFive Challenge Calls for RISC-V Hardware Innovations
• SiFive invested by Intel
  • SiFive Announces Investment from Intel Capital
• HiFive Expansion Board
  • HiFive Unleashed Expansion Board
  • Expansion Board Enhances Popular RISC-V Development Board
• Esperanto RISC-V Processor 改为专题报道
  • RISC-V processors make play for AI in Barcelona, says Esperanto
  • UltraSoC analytics IP selected by Esperanto Technologies for RISC-V many-core parallel processing in AI and ML applications
  • Partners Pump SoCs For AI

Maillist

• RISC-V Security Analysis Paper / Talk: Link
  (Wei: I wonder what really happened in this thread. For one moment, David Patterson is pretty pissed about something. It might not be related to this security talk at all. In fact, Don did not give a talk about RISC-V in the April conference as he had planned.) ＠待認領
• Trigonometric functions on risc-v. (Powei:Focus on how other ISA like Intel SSE optimize for it and find its impact on risc-v. Palmer's response might be helpful. fuwei
• [sw-dev] Why are VPN and PPN of different size in Virtual Memory System ? link (Wei: This is a rather interesting question and easy to start with. I suggest our new editors to start with this one.) @poweihuang17
• [isa-dev] Reserved space in C.LWSP, is Spike still the golden reference or is it Rocket? was: Re: /a/groups.riscv.org/d/msg/isa-dev/oT1r-owKicY/NoP0GTEHAwAJ) (Wei: an interesting case where backwards compatibility wins over a potential clarification of the spec. Also an easy one to report.) @容威

Eco

• Pulpino simulation update. weiwei

Code Update

• Updates to the memory consistency model spec: Updates to the memory consistency model spec riscv/riscv-isa-manual#166 @poweihuang17