Separate build and test for python runner

Ability to “easy” parallel runs

cocotb/runner.py

@@ -46,6 +46,8 @@ def __init__(self) -> None:
         self.simulator_in_path()
 
         self.env: Dict[str, str] = {}
+        self.build_dir = "sim_build"
+        self.library_name = "work"
 
     @abc.abstractmethod
     def simulator_in_path(self) -> None:
@@ -79,9 +81,6 @@ def set_env(self) -> None:
         self.env["TOPLEVEL"] = self.sim_toplevel
         self.env["MODULE"] = self.module
 
-        if not os.path.exists(self.build_dir):
-            os.makedirs(self.build_dir)
-
     @abc.abstractmethod
     def build_command(self) -> Sequence[Command]:
         """Return command to build the HDL sources."""
@@ -145,12 +144,20 @@ def test(
         extra_env: Mapping[str, str] = {},
         waves: Optional[bool] = None,
         gui: Optional[bool] = None,
+        library_name : Optional[str] = None,
+        build_dir: Optional[PathLike] = None,
         sim_dir: Optional[PathLike] = None,
     ) -> PathLike:
         """Run a test."""
 
         __tracebackhide__ = True  # Hide the traceback when using pytest
 
+        if build_dir is not None:
+            self.build_dir = build_dir
+
+        if library_name is not None:
+            self.library_name = library_name
+
         if sim_dir is None:
             self.sim_dir = self.build_dir
         else:
@@ -342,6 +349,10 @@ def get_parameter_options(self, parameters: Mapping[str, object]) -> List[str]:
             for name, value in parameters.items()
         ]
 
+    @property
+    def sim_file(self):
+        return os.path.join(self.build_dir, self.library_name + ".vvp")
+
     def test_command(self) -> List[Command]:
 
         return [
@@ -362,8 +373,6 @@ def build_command(self) -> List[Command]:
         if self.vhdl_sources:
             raise ValueError("This simulator does not support VHDL")
 
-        self.sim_file = os.path.join(self.build_dir, self.library_name + ".vvp")
-
         cmd = []
         if outdated(self.sim_file, self.verilog_sources) or self.always:
 

tests/pytest/test_cocotb.py

@@ -27,43 +27,44 @@
     "test_timing_triggers"
 ]
 
+verilog_sources = []
+vhdl_sources = []
+toplevel_lang = os.getenv("TOPLEVEL_LANG", "verilog")
 
-def test_cocotb():
-    verilog_sources = []
-    vhdl_sources = []
-    toplevel_lang = os.getenv("TOPLEVEL_LANG", "verilog")
+if toplevel_lang == "verilog":
+    verilog_sources=[
+        os.path.join(tests_dir, "designs", "sample_module", "sample_module.sv")
+    ]
+else:
+    vhdl_sources=[
+        os.path.join(tests_dir, "designs", "sample_module", "sample_module_pack.vhdl"),
+        os.path.join(tests_dir, "designs", "sample_module", "sample_module_1.vhdl"),
+        os.path.join(tests_dir, "designs", "sample_module", "sample_module.vhdl")
+    ]
 
-    if toplevel_lang == "verilog":
-        verilog_sources=[
-            os.path.join(tests_dir, "designs", "sample_module", "sample_module.sv")
-        ]
-    else:
-        vhdl_sources=[
-            os.path.join(tests_dir, "designs", "sample_module", "sample_module_pack.vhdl"),
-            os.path.join(tests_dir, "designs", "sample_module", "sample_module_1.vhdl"),
-            os.path.join(tests_dir, "designs", "sample_module", "sample_module.vhdl")
-        ]
+sim = os.getenv("SIM", "icarus")
+sim_args = ["-t", "ps"] if sim == "questa" else []
+compile_args = ["+acc"] if sim == "questa" else []
+toplevel="sample_module"
+python_search=[os.path.join(tests_dir, "test_cases", "test_cocotb")]
 
-    sim = os.getenv("SIM", "icarus")
+def test_cocotb():
+
     runner = get_runner(sim)()
 
-    compile_args = ["+acc"] if sim == "questa" else []
-
     runner.build(
         verilog_sources=verilog_sources,
         vhdl_sources=vhdl_sources,
-        toplevel="sample_module",
+        toplevel=toplevel,
         build_dir=sim_build,
         extra_args=compile_args)
-    sim_args = ["-t", "ps"] if sim == "questa" else []
-
+
     runner.test(
         toplevel_lang=toplevel_lang,
-        python_search=[os.path.join(tests_dir, "test_cases", "test_cocotb")],
-        toplevel="sample_module",
+        python_search=python_search,
+        toplevel=toplevel,
         py_module=module_name,
         extra_args=sim_args)
 
-
 if __name__ == "__main__":
     test_cocotb()

tests/pytest/test_paraller_cocotb.py

@@ -0,0 +1,35 @@
+# Copyright cocotb contributors
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+from cocotb.runner import get_runner
+import pytest
+
+from test_cocotb import sim_build, module_name, verilog_sources, vhdl_sources, toplevel_lang, toplevel, sim, compile_args, sim_args, python_search
+
+@pytest.mark.compile
+def test_cocotb_paraller_compile():
+
+    runner = get_runner(sim)()
+
+    runner.build(
+        always=True,
+        verilog_sources=verilog_sources,
+        vhdl_sources=vhdl_sources,
+        toplevel=toplevel,
+        build_dir=sim_build,
+        extra_args=compile_args)
+
+@pytest.mark.parametrize("seed", list(range(4)))
+def test_cocotb_paraller(seed):
+
+    runner = get_runner(sim)()
+
+    runner.test(
+        seed=seed,
+        toplevel_lang=toplevel_lang,
+        python_search=python_search,
+        toplevel=toplevel,
+        py_module=module_name,
+        extra_args=sim_args,
+        build_dir=sim_build)