Merge pull request #1075 from cmarqu/add-vhdl93-flag

Add flag to compile as VHDL93 for IUS/Xcelium for some designs
cocotb · Aug 19, 2019 · ddcd4b2 · ddcd4b2
2 parents 7de14fb + 877e0c8
commit ddcd4b2
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Showing 3 changed files with 14 additions and 2 deletions.
diff --git a/tests/designs/uart2bus/Makefile b/tests/designs/uart2bus/Makefile
@@ -36,6 +36,10 @@ VERILOG_SOURCES =   $(SRC_BASE)/verilog/baud_gen.v \
 VERILOG_SOURCES += $(SRC_BASE)/top/verilog_toplevel.sv
 TOPLEVEL = verilog_toplevel
 
+ifeq ($(SIM),$(filter $(SIM),ius xcelium))
+    SIM_ARGS += -v93
+endif
+
 include $(COCOTB)/makefiles/Makefile.inc
 include $(COCOTB)/makefiles/Makefile.sim
 

diff --git a/tests/designs/vhdl_configurations/Makefile b/tests/designs/vhdl_configurations/Makefile
@@ -28,12 +28,16 @@ VHDL_SOURCES = $(COCOTB)/tests/designs/vhdl_configurations/dut.vhd
 ifeq ($(TOPLEVEL_LANG),verilog)
     VERILOG_SOURCES = $(COCOTB)/tests/designs/vhdl_configurations/testbench.sv
 else ifeq ($(TOPLEVEL_LANG),vhdl)
-   	VHDL_SOURCES += $(COCOTB)/tests/designs/vhdl_configurations/testbench.vhd
+    VHDL_SOURCES += $(COCOTB)/tests/designs/vhdl_configurations/testbench.vhd
 else
     $(error "A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG)")
 endif
 VHDL_SOURCES += $(COCOTB)/tests/designs/vhdl_configurations/configurations.vhd
 
+ifeq ($(SIM),$(filter $(SIM),ius xcelium))
+    SIM_ARGS += -v93
+endif
+
 include $(COCOTB)/makefiles/Makefile.inc
 include $(COCOTB)/makefiles/Makefile.sim
 

diff --git a/tests/designs/viterbi_decoder_axi4s/Makefile b/tests/designs/viterbi_decoder_axi4s/Makefile
@@ -63,7 +63,11 @@ VHDL_SOURCES = $(SRC_BASE)/packages/pkg_helper.vhd \
 	       $(SRC_BASE)/src/ram_ctrl.vhd \
 	       $(SRC_BASE)/src/reorder.vhd \
 	       $(SRC_BASE)/src/recursion.vhd \
-	       $(SRC_BASE)/src/dec_viterbi.vhd \
+	       $(SRC_BASE)/src/dec_viterbi.vhd
+
+ifeq ($(SIM),$(filter $(SIM),ius xcelium))
+    SIM_ARGS += -v93
+endif
 
 include $(COCOTB)/makefiles/Makefile.inc
 include $(COCOTB)/makefiles/Makefile.sim