Verilog Code for the UFCache project. Presentation video is available here
UFCache is a new cache memory system which uses capacities as timers to check the data from the memory blocks. Instead of using software, we adapted the LRU algorithm and implemented it using hardware modules. Check the datasheet for more details.
In the app there are implemented the following features:
- Time
- Faster reads
- Simple algoritm
- Uses residual capacities of MOS transistors (which usually consists an issue in electronic circuits)
- Uses energy from the pins where signals were received
Install Vivado and open the .xpr file. Then press run from the tab menu.
For the moment, the application is quite simple and it needs improvement. Some of the features proposed are:
- Multicore processor scenario
- Wiring design