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disas.nim
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disas.nim
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import armtypes, armfuncs, types, funcs
import allAC
include "ltgt"
template ctxspec(TAsmCtx : typedesc, TVal : typedesc, TRVal : typedesc) =
proc processInsn16*(ctx : TAsmCtx, insn : TBinary, t : TInsnFlags) : TVal =
# []
if bit(insn, 15):
# [(15, 1)]
if bit(insn, 14):
# [(15, 1), (14, 1)]
if bit(insn, 13):
# [(15, 1), (14, 1), (13, 1)]
if not bit(insn, 12):
# [(15, 1), (14, 1), (13, 1), (12, 0)]
if not bit(insn, 11):
# [(15, 1), (14, 1), (13, 1), (12, 0), (11, 0)]
# [(15, 1), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2)]
# [(15, 1), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2)]
# [(15, 1), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2)]
# [(15, 1), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 1), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 1), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x10048b248>
#B<c> <label>
#(1, 1, 1, 0, 0, None, None, None, None, None, None, None, None, None, None, None)
block:
var imm11 : TBinary = insn[10,0]
return ctx.opB({}, <(sxt(cat(imm11, b"0"))))
nil
else: #13
# [(15, 1), (14, 1), (13, 0)]
if bit(insn, 12):
# [(15, 1), (14, 1), (13, 0), (12, 1)]
if bit(insn, 11):
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 1)]
if bit(insn, 10):
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1)]
if bit(insn, 9):
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1)]
if bit(insn, 8):
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2), (6, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004af4d0>
#SVC<c> #<imm8>
#(1, 1, 0, 1, 1, 1, 1, 1, None, None, None, None, None, None, None, None)
block:
var imm8 : TBinary = insn[7,0]
return ctx.opSVC({}, <imm8)
nil
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 2), (10, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 2), (10, 2), (9, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 2), (10, 2), (9, 2), (8, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 2), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 2), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 2), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 2), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 2), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 2), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 1), (11, 2), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x10048b1b8>
#B<c> <label>
#(1, 1, 0, 1, None, None, None, None, None, None, None, None, None, None, None, None)
block:
var cond : TBinary = insn[11,8]
var imm8 : TBinary = insn[7,0]
return ctx.opB(fromCond(cond), <(sxt(cat(imm8, b"0"))))
nil
else: #12
# [(15, 1), (14, 1), (13, 0), (12, 0)]
if bit(insn, 11):
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 1)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004919e0>
#LDM<c> <Rn>,<registers> <Rn> included in <registers>
#(1, 1, 0, 0, 1, None, None, None, None, None, None, None, None, None, None, None)
block:
var Rn : TReg = TReg(insn[10,8].num)
var register_list : TBinary = insn[7,0]
var rl = cat(b"00000000", register_list)
if rl[int(Rn)].bit:
#rl = rl.bclear(int(rn))
return ctx.opLDM({}, <Rn, ctx.RegList(rl))
else:
return ctx.opLDMIA({}, >Rn, ctx.RegList(rl))
nil
else: #11
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 0)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 0), (10, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 1), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004a8b00>
#STM<c> <Rn>!,<registers>
#(1, 1, 0, 0, 0, None, None, None, None, None, None, None, None, None, None, None)
block:
var Rn : TReg = TReg(insn[10,8].num)
var register_list : TBinary = insn[7,0]
var rl = cat(b"00000000", register_list)
if rl[int(Rn)].bit:
return ctx.opSTM({}, <Rn, ctx.RegList(rl))
else:
return ctx.opSTMIA({}, >Rn, ctx.RegList(rl))
nil
else: #14
# [(15, 1), (14, 0)]
if bit(insn, 13):
# [(15, 1), (14, 0), (13, 1)]
if bit(insn, 12):
# [(15, 1), (14, 0), (13, 1), (12, 1)]
if bit(insn, 11):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1)]
if bit(insn, 10):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1)]
if bit(insn, 9):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1)]
if bit(insn, 8):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1)]
if not bit(insn, 7):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0)]
if bit(insn, 6):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 1)]
if not bit(insn, 5):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 1), (5, 0)]
if not bit(insn, 4):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 1), (5, 0), (4, 0)]
if not bit(insn, 3):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 1), (5, 0), (4, 0), (3, 0)]
if not bit(insn, 2):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 1), (5, 0), (4, 0), (3, 0), (2, 0)]
if not bit(insn, 1):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 1), (5, 0), (4, 0), (3, 0), (2, 0), (1, 0)]
if not bit(insn, 0):
#i: <__main__.instruction instance at 0x1004a86c8>
#SEV<c>
#(1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0)
block:
return ctx.opSEV({})
nil
else: #6
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0)]
if bit(insn, 5):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 1)]
if bit(insn, 4):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 1), (4, 1)]
if not bit(insn, 3):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 1), (4, 1), (3, 0)]
if not bit(insn, 2):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 1), (4, 1), (3, 0), (2, 0)]
if not bit(insn, 1):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 1), (4, 1), (3, 0), (2, 0), (1, 0)]
if not bit(insn, 0):
#i: <__main__.instruction instance at 0x1004b44d0>
#WFI<c>
#(1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0)
block:
return ctx.opWFI({})
nil
else: #4
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 1), (4, 0)]
if not bit(insn, 3):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 1), (4, 0), (3, 0)]
if not bit(insn, 2):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 1), (4, 0), (3, 0), (2, 0)]
if not bit(insn, 1):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 1), (4, 0), (3, 0), (2, 0), (1, 0)]
if not bit(insn, 0):
#i: <__main__.instruction instance at 0x1004b43b0>
#WFE<c>
#(1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0)
block:
return ctx.opWFE({})
nil
else: #5
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 0)]
if bit(insn, 4):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 0), (4, 1)]
if not bit(insn, 3):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 0), (4, 1), (3, 0)]
if not bit(insn, 2):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 0), (4, 1), (3, 0), (2, 0)]
if not bit(insn, 1):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 0), (4, 1), (3, 0), (2, 0), (1, 0)]
if not bit(insn, 0):
#i: <__main__.instruction instance at 0x1004b45f0>
#YIELD<c>
#(1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0)
block:
return ctx.opYIELD({})
nil
else: #4
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 0), (4, 0)]
if not bit(insn, 3):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 0), (4, 0), (3, 0)]
if not bit(insn, 2):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 0), (4, 0), (3, 0), (2, 0)]
if not bit(insn, 1):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 0), (6, 0), (5, 0), (4, 0), (3, 0), (2, 0), (1, 0)]
if not bit(insn, 0):
#i: <__main__.instruction instance at 0x10049ddd0>
#NOP<c>
#(1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0)
block:
return ctx.opNOP({})
nil
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2), (6, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 1), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x100491710>
#IT{x{y{z}}} <firstcond>
#(1, 0, 1, 1, 1, 1, 1, 1, None, None, None, None, None, None, None, None)
block:
var firstcond : TBinary = insn[7,4]
var mask : TBinary = insn[3,0]
# Yuk. This will need special care.
if mask == b"0000": break
return ctx.opIT(fromCond(firstcond), ctx.ITarg(parseIT(TCond(firstcond.num), mask)))
nil
else: #8
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 0)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 0), (7, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 0), (7, 2), (6, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 0), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 0), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 0), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 0), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 1), (8, 0), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x10048b758>
#BKPT #<imm8>
#(1, 0, 1, 1, 1, 1, 1, 0, None, None, None, None, None, None, None, None)
block:
var imm8 : TBinary = insn[7,0]
return ctx.opBKPT({}, <imm8)
nil
else: #9
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 0)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004a0830>
#POP<c> <registers>
#(1, 0, 1, 1, 1, 1, 0, None, None, None, None, None, None, None, None, None)
block:
var P : TBinary = insn[8,8]
var register_list : TBinary = insn[7,0]
return ctx.opLDMIA({}, >SP, ctx.RegList(cat(P, b"0000000", register_list)))
nil
else: #10
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0)]
if bit(insn, 9):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1)]
if not bit(insn, 8):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0)]
if bit(insn, 7):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 1)]
if bit(insn, 6):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 1), (6, 1)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 1), (6, 1), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 1), (6, 1), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 1), (6, 1), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 1), (6, 1), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 1), (6, 1), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004a0d88>
#REVSH<c> <Rd>,<Rm>
#(1, 0, 1, 1, 1, 0, 1, 0, 1, 1, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[5,3].num)
var Rd : TReg = TReg(insn[2,0].num)
return ctx.opREVSH({}, >Rd, <Rm)
nil
else: #7
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0)]
if bit(insn, 6):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0), (6, 1)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0), (6, 1), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0), (6, 1), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0), (6, 1), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0), (6, 1), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0), (6, 1), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004a0c68>
#REV16<c> <Rd>,<Rm>
#(1, 0, 1, 1, 1, 0, 1, 0, 0, 1, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[5,3].num)
var Rd : TReg = TReg(insn[2,0].num)
return ctx.opREV16({}, >Rd, <Rm)
nil
else: #6
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0), (6, 0)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0), (6, 0), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0), (6, 0), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0), (6, 0), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0), (6, 0), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 1), (10, 0), (9, 1), (8, 0), (7, 0), (6, 0), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004a0b48>
#REV<c> <Rd>,<Rm>
#(1, 0, 1, 1, 1, 0, 1, 0, 0, 0, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[5,3].num)
var Rd : TReg = TReg(insn[2,0].num)
return ctx.opREV({}, >Rd, <Rm)
nil
else: #11
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0)]
if bit(insn, 10):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1)]
if bit(insn, 9):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 1)]
if not bit(insn, 8):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 1), (8, 0)]
if not bit(insn, 7):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 1), (8, 0), (7, 0)]
if bit(insn, 6):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 1), (8, 0), (7, 0), (6, 1)]
if bit(insn, 5):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 1), (8, 0), (7, 0), (6, 1), (5, 1)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 1), (8, 0), (7, 0), (6, 1), (5, 1), (4, 2)]
if not bit(insn, 3):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 1), (8, 0), (7, 0), (6, 1), (5, 1), (4, 2), (3, 0)]
if not bit(insn, 2):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 1), (8, 0), (7, 0), (6, 1), (5, 1), (4, 2), (3, 0), (2, 0)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 1), (8, 0), (7, 0), (6, 1), (5, 1), (4, 2), (3, 0), (2, 0), (1, 2)]
#i: <__main__.instruction instance at 0x1004911b8>
#CPS<effect> <iflags>
#(1, 0, 1, 1, 0, 1, 1, 0, 0, 1, 1, None, 0, 0, None, None)
block:
var im : TBinary = insn[4,4]
var I : TBinary = insn[1,1]
var F : TBinary = insn[0,0]
#nil # see B4-2
return ctx.opCPS(if not im.bit: {ifCPSIE} else: {}, ctx.CPSarg(I.bit, F.bit))
nil
else: #9
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 0)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004a0950>
#PUSH<c> <registers>
#(1, 0, 1, 1, 0, 1, 0, None, None, None, None, None, None, None, None, None)
block:
var M : TBinary = insn[8,8]
var register_list : TBinary = insn[7,0]
return ctx.opSTMIA({}, >SP, ctx.RegList(cat(b"0", M, b"0000000", register_list)))
nil
else: #10
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0)]
if bit(insn, 9):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1)]
if not bit(insn, 8):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0)]
if bit(insn, 7):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1)]
if bit(insn, 6):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1), (6, 1)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1), (6, 1), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1), (6, 1), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1), (6, 1), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1), (6, 1), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1), (6, 1), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004b40e0>
#UXTB<c> <Rd>,<Rm>
#(1, 0, 1, 1, 0, 0, 1, 0, 1, 1, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[5,3].num)
var Rd : TReg = TReg(insn[2,0].num)
return ctx.opUXTB({}, <Rd, <Rm)
nil
else: #6
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1), (6, 0)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1), (6, 0), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1), (6, 0), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1), (6, 0), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1), (6, 0), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 1), (6, 0), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004b4248>
#UXTH<c> <Rd>,<Rm>
#(1, 0, 1, 1, 0, 0, 1, 0, 1, 0, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[5,3].num)
var Rd : TReg = TReg(insn[2,0].num)
return ctx.opUXTH({}, >Rd, <Rm)
nil
else: #7
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0)]
if bit(insn, 6):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0), (6, 1)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0), (6, 1), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0), (6, 1), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0), (6, 1), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0), (6, 1), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0), (6, 1), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004af638>
#SXTB<c> <Rd>,<Rm>
#(1, 0, 1, 1, 0, 0, 1, 0, 0, 1, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[5,3].num)
var Rd : TReg = TReg(insn[2,0].num)
return ctx.opSXTB({}, <Rd, <Rm)
nil
else: #6
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0), (6, 0)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0), (6, 0), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0), (6, 0), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0), (6, 0), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0), (6, 0), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 1), (8, 0), (7, 0), (6, 0), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004af7a0>
#SXTH<c> <Rd>,<Rm>
#(1, 0, 1, 1, 0, 0, 1, 0, 0, 0, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[5,3].num)
var Rd : TReg = TReg(insn[2,0].num)
return ctx.opSXTH({}, >Rd, <Rm)
nil
else: #9
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0)]
if not bit(insn, 8):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0)]
if bit(insn, 7):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 1)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 1), (6, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 1), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 1), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 1), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 1), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 1), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004af200>
#SUB<c> SP,SP,#<imm7>
#(1, 0, 1, 1, 0, 0, 0, 0, 1, None, None, None, None, None, None, None)
block:
var imm7 : TBinary = insn[6,0]
return ctx.opSUB({}, >SP, <SP, <cat(imm7, b"00"))
nil
else: #7
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 0)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 0), (6, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 0), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 0), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 0), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 0), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 0), (10, 0), (9, 0), (8, 0), (7, 0), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x10043c7a0>
#ADD<c> SP,SP,#<imm7>
#(1, 0, 1, 1, 0, 0, 0, 0, 0, None, None, None, None, None, None, None)
block:
var imm7 : TBinary = insn[6,0]
return ctx.opADD({}, >SP, <SP, <cat(imm7, b"00"))
nil
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 2)]
if not bit(insn, 10):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 2), (10, 0)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 2), (10, 0), (9, 2)]
if bit(insn, 8):
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 2), (10, 0), (9, 2), (8, 1)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 2), (10, 0), (9, 2), (8, 1), (7, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 2), (10, 0), (9, 2), (8, 1), (7, 2), (6, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 2), (10, 0), (9, 2), (8, 1), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 2), (10, 0), (9, 2), (8, 1), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 2), (10, 0), (9, 2), (8, 1), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 2), (10, 0), (9, 2), (8, 1), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 1), (11, 2), (10, 0), (9, 2), (8, 1), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x10048ba28>
#CB{N}Z <Rn>,<label>
#(1, 0, 1, 1, None, 0, None, 1, None, None, None, None, None, None, None, None)
block:
var op : TBinary = insn[11,11]
var i : TBinary = insn[9,9]
var imm5 : TBinary = insn[7,3]
var Rn : TReg = TReg(insn[2,0].num)
var arg = <cat(i, imm5, b"0")
if op.bit:
return ctx.opCBNZ({}, <Rn, arg)
else:
return ctx.opCBZ({}, <Rn, arg)
nil
else: #12
# [(15, 1), (14, 0), (13, 1), (12, 0)]
if bit(insn, 11):
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 1)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 1), (10, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x10043c7e8>
#ADD<c> <Rd>,SP,#<imm8>
#(1, 0, 1, 0, 1, None, None, None, None, None, None, None, None, None, None, None)
block:
var Rd : TReg = TReg(insn[10,8].num)
var imm8 : TBinary = insn[7,0]
return ctx.opADD({}, >Rd, <SP, <cat(imm8, b"00"))
nil
else: #11
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 0)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 0), (10, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x10043cab8>
#ADR<c> <Rd>,<label>
#(1, 0, 1, 0, 0, None, None, None, None, None, None, None, None, None, None, None)
block:
var Rd : TReg = TReg(insn[10,8].num)
var imm8 : TBinary = insn[7,0]
return ctx.opADR({}, >Rd, <PC, <(cat(imm8, b"00").num))
nil
else: #13
# [(15, 1), (14, 0), (13, 0)]
if bit(insn, 12):
# [(15, 1), (14, 0), (13, 0), (12, 1)]
if bit(insn, 11):
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 1)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 1), (10, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 1), (10, 2), (9, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x100491cf8>
#LDR<c> <Rt>,[SP{,#<imm8>}]
#(1, 0, 0, 1, 1, None, None, None, None, None, None, None, None, None, None, None)
block:
var Rt : TReg = TReg(insn[10,8].num)
var imm8 : TBinary = insn[7,0]
return ctx.opLDR({}, >Rt, ctx.Deref(>SP, <cat(imm8, b"00"), 4, true, false, true))
nil
else: #11
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 0)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 0), (10, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 0), (10, 2), (9, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004a8dd0>
#STR<c> <Rt>,[SP,#<imm8>]
#(1, 0, 0, 1, 0, None, None, None, None, None, None, None, None, None, None, None)
block:
var Rt : TReg = TReg(insn[10,8].num)
var imm8 : TBinary = insn[7,0]
return ctx.opSTR({}, <Rt, ctx.Deref(>SP, <cat(imm8, b"00"), 4, true, false, true))
nil
else: #12
# [(15, 1), (14, 0), (13, 0), (12, 0)]
if bit(insn, 11):
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 1)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 1), (10, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x100495a28>
#LDRH<c> <Rt>,[<Rn>{,#<imm5>}]
#(1, 0, 0, 0, 1, None, None, None, None, None, None, None, None, None, None, None)
block:
var imm5 : TBinary = insn[10,6]
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opLDRH({}, >Rt, ctx.Deref(>Rn, <cat(imm5, b"0"), 2, true, false, true))
nil
else: #11
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 0)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 0), (10, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 1), (14, 0), (13, 0), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004ab908>
#STRH<c> <Rt>,[<Rn>{,#<imm5>}]
#(1, 0, 0, 0, 0, None, None, None, None, None, None, None, None, None, None, None)
block:
var imm5 : TBinary = insn[10,6]
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opSTRH({}, <Rt, ctx.Deref(>Rn, <cat(imm5, b"0"), 2, true, false, true))
nil
else: #15
# [(15, 0)]
if bit(insn, 14):
# [(15, 0), (14, 1)]
if bit(insn, 13):
# [(15, 0), (14, 1), (13, 1)]
if bit(insn, 12):
# [(15, 0), (14, 1), (13, 1), (12, 1)]
if bit(insn, 11):
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 1)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 1), (10, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 1), (10, 2), (9, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x100495200>
#LDRB<c> <Rt>,[<Rn>{,#<imm5>}]
#(0, 1, 1, 1, 1, None, None, None, None, None, None, None, None, None, None, None)
block:
var imm5 : TBinary = insn[10,6]
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opLDRB({}, >Rt, ctx.Deref(>Rn, <imm5, 1, true, false, true))
nil
else: #11
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 0)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 0), (10, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 0), (10, 2), (9, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 1), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004ab1b8>
#STRB<c> <Rt>,[<Rn>,#<imm5>]
#(0, 1, 1, 1, 0, None, None, None, None, None, None, None, None, None, None, None)
block:
var imm5 : TBinary = insn[10,6]
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opSTRB({}, <Rt, ctx.Deref(>Rn, <imm5, 1, true, false, true))
nil
else: #12
# [(15, 0), (14, 1), (13, 1), (12, 0)]
if bit(insn, 11):
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 1)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 1), (10, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x100491b90>
#LDR<c> <Rt>, [<Rn>{,#<imm5>}]
#(0, 1, 1, 0, 1, None, None, None, None, None, None, None, None, None, None, None)
block:
var imm5 : TBinary = insn[10,6]
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opLDR({}, >Rt, ctx.Deref(>Rn, <cat(imm5, b"00"), 4, true, false, true))
nil
else: #11
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 0)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 1), (12, 0), (11, 0), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004a8d40>
#STR<c> <Rt>, [<Rn>{,#<imm5>}]
#(0, 1, 1, 0, 0, None, None, None, None, None, None, None, None, None, None, None)
block:
var imm5 : TBinary = insn[10,6]
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opSTR({}, <Rt, ctx.Deref(>Rn, <cat(imm5, b"00"), 4, true, false, true))
nil
else: #13
# [(15, 0), (14, 1), (13, 0)]
if bit(insn, 12):
# [(15, 0), (14, 1), (13, 0), (12, 1)]
if bit(insn, 11):
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1)]
if bit(insn, 10):
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1)]
if bit(insn, 9):
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x100499638>
#LDRSH<c> <Rt>,[<Rn>,<Rm>]
#(0, 1, 0, 1, 1, 1, 1, None, None, None, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[8,6].num)
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opLDRSH({}, >Rt, ctx.Deref(<Rn, <Rm, 2, true, false, true))
nil
else: #9
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 0)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x100495488>
#LDRB<c> <Rt>,[<Rn>,<Rm>]
#(0, 1, 0, 1, 1, 1, 0, None, None, None, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[8,6].num)
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opLDRB({}, >Rt, ctx.Deref(>Rn, <Rm, 1, true, false, true))
nil
else: #10
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0)]
if bit(insn, 9):
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 1)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 1), (8, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 1), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 1), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x100495cb0>
#LDRH<c> <Rt>,[<Rn>,<Rm>]
#(0, 1, 0, 1, 1, 0, 1, None, None, None, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[8,6].num)
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opLDRH({}, >Rt, ctx.Deref(<Rn, <Rm, 2, true, false, true))
nil
else: #9
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 0)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 0), (8, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 0), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 0), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 1), (10, 0), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x100495050>
#LDR<c> <Rt>,[<Rn>,<Rm>]
#(0, 1, 0, 1, 1, 0, 0, None, None, None, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[8,6].num)
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opLDR({}, >Rt, ctx.Deref(>Rn, <Rm, 4, true, false, true))
nil
else: #11
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0)]
if bit(insn, 10):
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1)]
if bit(insn, 9):
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 1)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 1), (8, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 1), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 1), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004991b8>
#LDRSB<c> <Rt>,[<Rn>,<Rm>]
#(0, 1, 0, 1, 0, 1, 1, None, None, None, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[8,6].num)
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opLDRSB({}, >Rt, ctx.Deref(>Rn, <Rm, 1, true, false, true))
nil
else: #9
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 0)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 1), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004ab3b0>
#STRB<c> <Rt>,[<Rn>,<Rm>]
#(0, 1, 0, 1, 0, 1, 0, None, None, None, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[8,6].num)
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opSTRB({}, <Rt, ctx.Deref(>Rn, <Rm, 1, true, false, true))
nil
else: #10
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0)]
if bit(insn, 9):
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 1)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 1), (8, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 1), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 1), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 1), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004abb00>
#STRH<c> <Rt>,[<Rn>,<Rm>]
#(0, 1, 0, 1, 0, 0, 1, None, None, None, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[8,6].num)
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
if Rt == PC: break
return ctx.opSTRH({}, <Rt, ctx.Deref(<Rn, <Rm, 2, true, false, true))
nil
else: #9
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 0)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 0), (8, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 0), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 0), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 1), (11, 0), (10, 0), (9, 0), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x1004ab050>
#STR<c> <Rt>,[<Rn>,<Rm>]
#(0, 1, 0, 1, 0, 0, 0, None, None, None, None, None, None, None, None, None)
block:
var Rm : TReg = TReg(insn[8,6].num)
var Rn : TReg = TReg(insn[5,3].num)
var Rt : TReg = TReg(insn[2,0].num)
return ctx.opSTR({}, <Rt, ctx.Deref(>Rn, <Rm, 4, true, false, true))
nil
else: #12
# [(15, 0), (14, 1), (13, 0), (12, 0)]
if bit(insn, 11):
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 1)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 1), (10, 2), (9, 2), (8, 2), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x100491ef0>
#LDR<c> <Rt>,<label>
#(0, 1, 0, 0, 1, None, None, None, None, None, None, None, None, None, None, None)
block:
var Rt : TReg = TReg(insn[10,8].num)
var imm8 : TBinary = insn[7,0]
return ctx.opLDR({}, >Rt, ctx.Deref(>PC, <cat(imm8, b"00"), 4, true, false, true))
nil
else: #11
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0)]
if bit(insn, 10):
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1)]
if bit(insn, 9):
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1)]
if bit(insn, 8):
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1)]
if bit(insn, 7):
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 1)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 1), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 1), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 1), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 1), (6, 2), (5, 2), (4, 2), (3, 2)]
if not bit(insn, 2):
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 1), (6, 2), (5, 2), (4, 2), (3, 2), (2, 0)]
if not bit(insn, 1):
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 1), (6, 2), (5, 2), (4, 2), (3, 2), (2, 0), (1, 0)]
if not bit(insn, 0):
#i: <__main__.instruction instance at 0x10048b878>
#BLX<c> <Rm>
#(0, 1, 0, 0, 0, 1, 1, 1, 1, None, None, None, None, 0, 0, 0)
block:
var Rm : TReg = TReg(insn[6,3].num)
return ctx.opBLX({}, <Rm)
nil
else: #7
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 0)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 0), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 0), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 0), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 0), (6, 2), (5, 2), (4, 2), (3, 2)]
if not bit(insn, 2):
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 0), (6, 2), (5, 2), (4, 2), (3, 2), (2, 0)]
if not bit(insn, 1):
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 1), (7, 0), (6, 2), (5, 2), (4, 2), (3, 2), (2, 0), (1, 0)]
if not bit(insn, 0):
#i: <__main__.instruction instance at 0x10048b908>
#BX<c> <Rm>
#(0, 1, 0, 0, 0, 1, 1, 1, 0, None, None, None, None, 0, 0, 0)
block:
var Rm : TReg = TReg(insn[6,3].num)
return ctx.opBX({}, <Rm)
nil
else: #8
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 0)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 0), (7, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 0), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 0), (7, 2), (6, 2), (5, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 0), (7, 2), (6, 2), (5, 2), (4, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 0), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 0), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 1), (8, 0), (7, 2), (6, 2), (5, 2), (4, 2), (3, 2), (2, 2), (1, 2)]
#i: <__main__.instruction instance at 0x10049d488>
#MOV<c> <Rd>,<Rm>
#(0, 1, 0, 0, 0, 1, 1, 0, None, None, None, None, None, None, None, None)
block:
var D : TBinary = insn[7,7]
var Rm : TReg = TReg(insn[6,3].num)
var Rd : TReg = TReg(insn[2,0].num)
return ctx.opMOV(t, >Rd, <Rm)
nil
else: #9
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 0)]
if bit(insn, 8):
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 0), (8, 1)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 0), (8, 1), (7, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 0), (8, 1), (7, 2), (6, 2)]
# [(15, 0), (14, 1), (13, 0), (12, 0), (11, 0), (10, 1), (9, 0), (8, 1), (7, 2), (6, 2), (5, 2)]