soc/intel/baytrail: Get rid of device_t

Use of device_t has been abandoned in ramstage. Change-Id: I8b2cfe3e2090fb8eed755e40d337c6049d8dd96e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
coreboot · May 24, 2018 · 17a3ceb · 17a3ceb
1 parent 148b1db
commit 17a3ceb
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Showing 18 changed files with 68 additions and 62 deletions.
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
@@ -443,7 +443,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	acpigen_pop_len();
 }
 
-void generate_cpu_entries(device_t device)
+void generate_cpu_entries(struct device *device)
 {
 	int core;
 	int pcontrol_blk = get_pmbase(), plen = 6;

diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c
@@ -22,7 +22,7 @@
 #include <soc/ramstage.h>
 #include "chip.h"
 
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
 {
 	assign_resources(dev->link_list);
 }
@@ -44,7 +44,7 @@ static struct device_operations cpu_bus_ops = {
 };
 
 
-static void enable_dev(device_t dev)
+static void enable_dev(struct device *dev)
 {
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_DOMAIN) {
@@ -72,7 +72,8 @@ struct chip_operations soc_intel_baytrail_ops = {
 	.init = soc_init,
 };
 
-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pci_set_subsystem(struct device *dev, unsigned vendor,
+			      unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,

diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
@@ -44,7 +44,7 @@ const struct reg_script core_msr_script[] = {
 	REG_SCRIPT_END
 };
 
-static void baytrail_core_init(device_t cpu)
+static void baytrail_core_init(struct device *cpu)
 {
 	printk(BIOS_DEBUG, "Init BayTrail core.\n");
 
@@ -199,7 +199,7 @@ static const struct mp_ops mp_ops = {
 	.post_mp_init = southcluster_smm_enable_smi,
 };
 
-void baytrail_init_cpus(device_t dev)
+void baytrail_init_cpus(struct device *dev)
 {
 	struct bus *cpu_bus = dev->link_list;
 

diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c
@@ -87,7 +87,7 @@ static const struct reg_script ehci_hc_reset[] = {
 	REG_SCRIPT_END
 };
 
-static void usb2_phy_init(device_t dev)
+static void usb2_phy_init(struct device *dev)
 {
 	struct soc_intel_baytrail_config *config = dev->chip_info;
 	u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ?
@@ -122,7 +122,7 @@ static void usb2_phy_init(device_t dev)
 	reg_script_run(usb2_phy_script);
 }
 
-static void ehci_init(device_t dev)
+static void ehci_init(struct device *dev)
 {
 	struct soc_intel_baytrail_config *config = dev->chip_info;
 	struct reg_script ehci_hc_init[] = {

diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c
@@ -45,7 +45,7 @@ static const struct reg_script emmc_ops[] = {
 	REG_SCRIPT_END,
 };
 
-static void emmc_init(device_t dev)
+static void emmc_init(struct device *dev)
 {
 	struct soc_intel_baytrail_config *config = dev->chip_info;
 

diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
@@ -38,7 +38,7 @@
  * Lock Power Context Base Register to point to a 24KB block
  * of memory in GSM.  Power context save data is stored here.
  */
-static void gfx_lock_pcbase(device_t dev)
+static void gfx_lock_pcbase(struct device *dev)
 {
 	struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256,
@@ -263,18 +263,19 @@ static const struct reg_script gfx_post_vbios_script[] = {
 	REG_SCRIPT_END
 };
 
-static inline void gfx_run_script(device_t dev, const struct reg_script *ops)
+static inline void gfx_run_script(struct device *dev,
+				  const struct reg_script *ops)
 {
 	reg_script_run_on_dev(dev, ops);
 }
 
-static void gfx_pre_vbios_init(device_t dev)
+static void gfx_pre_vbios_init(struct device *dev)
 {
 	printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
 	gfx_run_script(dev, gpu_pre_vbios_script);
 }
 
-static void gfx_pm_init(device_t dev)
+static void gfx_pm_init(struct device *dev)
 {
 	printk(BIOS_INFO, "GFX: Power Management Init\n");
 	gfx_run_script(dev, gfx_init_script);
@@ -283,13 +284,13 @@ static void gfx_pm_init(device_t dev)
 	gfx_lock_pcbase(dev);
 }
 
-static void gfx_post_vbios_init(device_t dev)
+static void gfx_post_vbios_init(struct device *dev)
 {
 	printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
 	gfx_run_script(dev, gfx_post_vbios_script);
 }
 
-static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz)
+static void set_backlight_pwm(struct device *dev, uint32_t bklt_reg, int req_hz)
 {
 	int divider;
 	struct resource *res;
@@ -310,7 +311,7 @@ static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz)
 	write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16);
 }
 
-static void gfx_panel_setup(device_t dev)
+static void gfx_panel_setup(struct device *dev)
 {
 	struct soc_intel_baytrail_config *config = dev->chip_info;
 	struct reg_script gfx_pipea_init[] = {
@@ -378,7 +379,7 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
 		gnvs_ptr->aslb = aslb;
 }
 
-static void gfx_init(device_t dev)
+static void gfx_init(struct device *dev)
 {
 	/* Pre VBIOS Init */
 	gfx_pre_vbios_init(dev);

diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c
@@ -69,7 +69,7 @@ static const uint32_t hdmi_codec_verb_table[] = {
 	0x20671f58,
 };
 
-static void hda_init(device_t dev)
+static void hda_init(struct device *dev)
 {
 	struct resource *res;
 	int codec_mask;

diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h
@@ -22,16 +22,16 @@
 /* The baytrail_init_pre_device() function is called prior to device
  * initialization, but it's after console and cbmem has been reinitialized. */
 void baytrail_init_pre_device(struct soc_intel_baytrail_config *config);
-void baytrail_init_cpus(device_t dev);
+void baytrail_init_cpus(struct device *dev);
 void set_max_freq(void);
-void southcluster_enable_dev(device_t dev);
+void southcluster_enable_dev(struct device *dev);
 #if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)
 void baytrail_run_reference_code(void);
 #else
 static inline void baytrail_run_reference_code(void) {}
 #endif
 void baytrail_init_scc(void);
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
 
 extern struct pci_operations soc_pci_ops;
 

diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
@@ -41,7 +41,7 @@
 #define FIRMWARE_REG_BASE_C0 0x144000
 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
 
-static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
+static void assign_device_nvs(struct device *dev, u32 *field, unsigned index)
 {
 	struct resource *res;
 
@@ -50,7 +50,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
 		*field = res->base;
 }
 
-static void lpe_enable_acpi_mode(device_t dev)
+static void lpe_enable_acpi_mode(struct device *dev)
 {
 	static const struct reg_script ops[] = {
 		/* Disable PCI interrupt, enable Memory and Bus Master */
@@ -83,7 +83,7 @@ static void lpe_enable_acpi_mode(device_t dev)
 	reg_script_run_on_dev(dev, ops);
 }
 
-static void setup_codec_clock(device_t dev)
+static void setup_codec_clock(struct device *dev)
 {
 	uint32_t reg;
 	u32 *clk_reg;
@@ -121,7 +121,7 @@ static void setup_codec_clock(device_t dev)
 	write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
 }
 
-static void lpe_stash_firmware_info(device_t dev)
+static void lpe_stash_firmware_info(struct device *dev)
 {
 	struct resource *res;
 	struct resource *mmio;
@@ -147,7 +147,7 @@ static void lpe_stash_firmware_info(device_t dev)
 	}
 }
 
-static void lpe_init(device_t dev)
+static void lpe_init(struct device *dev)
 {
 	struct soc_intel_baytrail_config *config = dev->chip_info;
 
@@ -159,7 +159,7 @@ static void lpe_init(device_t dev)
 		lpe_enable_acpi_mode(dev);
 }
 
-static void lpe_read_resources(device_t dev)
+static void lpe_read_resources(struct device *dev)
 {
 	pci_dev_read_resources(dev);
 

diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
@@ -29,7 +29,8 @@
 
 #include "chip.h"
 
-static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
+static void dev_enable_acpi_mode(struct device *dev, int iosf_reg,
+				 int nvs_index)
 {
 	struct reg_script ops[] = {
 		/* Disable PCI interrupt, enable Memory and Bus Master */
@@ -66,7 +67,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
 	reg_script_run_on_dev(dev, ops);
 }
 
-static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)
+static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg)
 {
 	struct reg_script ops[] = {
 		REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg,
@@ -78,7 +79,7 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)
 	reg_script_run_on_dev(dev, ops);
 }
 
-static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
+static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
 {
 	*iosf_reg = -1;
 	*nvs_index = -1;
@@ -119,7 +120,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
 	}
 }
 
-static void i2c_disable_resets(device_t dev)
+static void i2c_disable_resets(struct device *dev)
 {
 	/* Release the I2C devices from reset. */
 	static const struct reg_script ops[] = {
@@ -146,7 +147,7 @@ static void i2c_disable_resets(device_t dev)
 	}
 }
 
-static void lpss_init(device_t dev)
+static void lpss_init(struct device *dev)
 {
 	struct soc_intel_baytrail_config *config = dev->chip_info;
 	int iosf_reg, nvs_index;

diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c
@@ -75,7 +75,7 @@ uint32_t nc_read_top_of_low_memory(void)
 	return tolm;
 }
 
-static void nc_read_resources(device_t dev)
+static void nc_read_resources(struct device *dev)
 {
 	unsigned long mmconf;
 	unsigned long bmbound;

diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
@@ -30,12 +30,12 @@
 static int pll_en_off;
 static uint32_t strpfusecfg;
 
-static inline int root_port_offset(device_t dev)
+static inline int root_port_offset(struct device *dev)
 {
 	return PCI_FUNC(dev->path.pci.devfn);
 }
 
-static inline int is_first_port(device_t dev)
+static inline int is_first_port(struct device *dev)
 {
 	return root_port_offset(dev) == PCIE_PORT1_FUNC;
 }
@@ -84,7 +84,7 @@ static const struct reg_script init_static_after_exit_latency[] = {
 	REG_SCRIPT_END,
 };
 
-static void byt_pcie_init(device_t dev)
+static void byt_pcie_init(struct device *dev)
 {
 	struct reg_script init_script[] = {
 		REG_SCRIPT_NEXT(init_static_before_exit_latency),
@@ -125,7 +125,7 @@ static const struct reg_script no_dev_behind_port[] = {
 	REG_SCRIPT_END,
 };
 
-static void check_port_enabled(device_t dev)
+static void check_port_enabled(struct device *dev)
 {
 	int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT;
 
@@ -151,7 +151,7 @@ static void check_port_enabled(device_t dev)
 	}
 }
 
-static u8 all_ports_no_dev_present(device_t dev)
+static u8 all_ports_no_dev_present(struct device *dev)
 {
 	u8 func;
 	u8 temp = dev->path.pci.devfn;
@@ -180,7 +180,7 @@ static u8 all_ports_no_dev_present(device_t dev)
 	return device_not_present;
 }
 
-static void check_device_present(device_t dev)
+static void check_device_present(struct device *dev)
 {
 	/* Set slot implemented. */
 	pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI);
@@ -204,7 +204,7 @@ static void check_device_present(device_t dev)
 	}
 }
 
-static void byt_pcie_enable(device_t dev)
+static void byt_pcie_enable(struct device *dev)
 {
 	if (is_first_port(dev)) {
 		struct soc_intel_baytrail_config *config = dev->chip_info;
@@ -226,7 +226,7 @@ static void byt_pcie_enable(device_t dev)
 	southcluster_enable_dev(dev);
 }
 
-static void byt_pciexp_scan_bridge(device_t dev)
+static void byt_pciexp_scan_bridge(struct device *dev)
 {
 	static const struct reg_script wait_for_link_active[] = {
 		REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000),
@@ -239,7 +239,8 @@ static void byt_pciexp_scan_bridge(device_t dev)
 	do_pci_scan_bridge(dev, pciexp_scan_bus);
 }
 
-static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did)
+static void pcie_root_set_subsystem(struct device *dev, unsigned vid,
+				    unsigned did)
 {
 	uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff);
 

diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
@@ -75,7 +75,7 @@ static const char *stepping_str[] = {
 
 static void fill_in_pattrs(void)
 {
-	device_t dev;
+	struct device *dev;
 	msr_t msr;
 	struct pattrs *attrs = (struct pattrs *)pattrs_get();
 

diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c
@@ -155,7 +155,7 @@ static void sata_init(struct device *dev)
 	pci_write_config32(dev, 0x98, reg32);
 }
 
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
 {
 	config_t *config = dev->chip_info;
 	u8  reg8;

diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c
@@ -83,7 +83,7 @@ void baytrail_init_scc(void)
 	reg_script_run(scc_after_dll);
 }
 
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
 {
 	struct reg_script ops[] = {
 		/* Disable PCI interrupt, enable Memory and Bus Master */