mb/ibm: Add 4 SPR sockets server board IBM SBP1

The IBM SBP1 is an evaluation platform.

It's utilising:
- 4 SPR sockets, having 16 DIMMs each
- 240C/480T at maximum
- 32x CPU PCIe slots
- 2x M.2 PCH PCIe slots
- Dual 200Gbit/s NIC
- SPI TPM

It has an AST2600 BMC for remote management.

It doesn't have:
- External facing USB ports
- Video outputs
- Audio codec

Test:
  The board boots to Linux 5.15 with all 480 cores available.
  All PCIe devices are working and no errors in ACPI.
  All 64 memory DIMMS are working and M.2 devices can be used.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73392
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/ibm/Kconfig

@@ -0,0 +1,15 @@
+if VENDOR_IBM
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/ibm/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/ibm/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "IBM"
+
+endif # VENDOR_IBM

src/mainboard/ibm/Kconfig.name

@@ -0,0 +1,2 @@
+config VENDOR_IBM
+	bool "IBM"

src/mainboard/ibm/sbp1/Kconfig

@@ -0,0 +1,39 @@
+if BOARD_IBM_SBP1
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_65536
+	select IPMI_KCS
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select MAINBOARD_USES_FSP2_0
+	select SOC_INTEL_SAPPHIRERAPIDS_SP
+	select SUPERIO_ASPEED_AST2400 # Check if AST2400 is compatible
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_USES_IFD_GBE_REGION
+
+config MAINBOARD_DIR
+	string
+	default "ibm/sbp1"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "SBP1"
+
+config FMDFILE
+	string
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config MAX_SOCKET
+	int
+	default 4
+
+config MAX_SOCKET_UPD
+	int
+	default 4
+
+config MAX_CPUS
+	int
+	default 480
+
+endif

src/mainboard/ibm/sbp1/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_IBM_SBP1
+	bool "SBP1"

src/mainboard/ibm/sbp1/Makefile.inc

@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+romstage-y += romstage.c
+ramstage-y += ramstage.c
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include

src/mainboard/ibm/sbp1/acpi/platform.asl

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
+Name (_S0, Package () // mandatory system state
+{
+	0x00, 0x00, 0x00, 0x00
+})
+
+Name (_S5, Package ()  // mandatory system state
+{
+	0x07, 0x00, 0x00, 0x00
+})
+
+/* Port 80 POST */
+OperationRegion (DBG0, SystemIO, 0x80, 0x02)
+Field (DBG0, ByteAcc, Lock, Preserve)
+{
+	IO80, 8,
+	IO81, 8
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Return (Package (){ 0, 0 })
+}

src/mainboard/ibm/sbp1/board.fmd

@@ -0,0 +1,11 @@
+FLASH@0xfc000000 64M {
+	SI_ALL@0x0 0x03000000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000 0x2fff000
+	}
+	RW_MRC_CACHE@0x3000000 0x10000
+	FMAP 0x800
+	RW_VPD(PRESERVE) 0x4000
+	RO_VPD(PRESERVE) 0x4000
+	COREBOOT(CBFS)
+}

src/mainboard/ibm/sbp1/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: IBM
+Board name: SBP1
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/ibm/sbp1/bootblock.c

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+
+#define ASPEED_SIO_PORT 0x2E
+#define PCR_DMI_LPCIOD  0x2770
+#define PCR_DMI_LPCIOE  0x2774
+
+void bootblock_mainboard_early_init(void)
+{
+	uint16_t lpciod = LPC_IOD_COMA_RANGE;
+	uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMA_EN);
+
+	/* Open IO windows: 0x3f8 for com1 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
+	/* LPC I/O enable: com1 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
+
+	/* Enable com1 (0x3f8) and superio (0x2e) */
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
+
+	const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
+	aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+}

src/mainboard/ibm/sbp1/devicetree.cb

@@ -0,0 +1,36 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/spr
+
+	device domain 0 on
+		device pci 16.3 off end # Serial controller: Intel Corporation Device 1be3
+
+		device pci 1f.0 on         # Intel device 1b81: PCH eSPI controller
+			chip superio/common
+				device pnp 2e.0 on
+					chip superio/aspeed/ast2400
+						register "use_espi" = "1"
+						device pnp 2e.2 on      # SUART1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.3 on      # SUART2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+					end
+				end
+			end
+			chip drivers/ipmi # BMC KCS
+				device pnp ca2.0 on end
+				register "bmc_i2c_address" = "0x20"
+				register "bmc_boot_timeout" = "60"
+			end
+			chip drivers/pc80/tpm # TPM
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.3 off end # Intel device 1bc8: PCH audio
+		device pci 1f.6 off end # Intel device 1bcb: PCH GbE controller
+	end
+end

src/mainboard/ibm/sbp1/dsdt.asl

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	// platform ACPI tables
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	// SPR-SP ACPI tables
+	#include <soc/intel/xeon_sp/spr/acpi/uncore.asl>
+
+	// LPC related entries
+	Scope (\_SB.PC00)
+	{
+		#include <soc/intel/xeon_sp/spr/acpi/pch.asl>
+	}
+}