mb/google/dragonegg: Add initial mainboard code support

This patch includes support for both ICL ES0 and ES1 samples.

Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md

TEST=Able to build and boot dragonegg.

Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/mainboard/google/dragonegg/Kconfig

@@ -0,0 +1,83 @@
+config BOARD_GOOGLE_BASEBOARD_DRAGONEGG
+	def_bool n
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_I2C_HID
+	select DRIVERS_SPI_ACPI
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_LPC
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_HAS_CHROMEOS
+	select SOC_INTEL_ICELAKE
+
+if BOARD_GOOGLE_BASEBOARD_DRAGONEGG
+
+config CHROMEOS
+	bool
+	default y
+	select GBB_FLAG_FORCE_MANUAL_RECOVERY
+
+config DEVICETREE
+	string
+	default "variants/baseboard/devicetree.cb"
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+# Select this option to enable use of cr50 SPI TPM on dragon egg.
+config DRAGONEGG_USE_SPI_TPM
+	bool
+	default y
+	select MAINBOARD_HAS_SPI_TPM_CR50
+	select MAINBOARD_HAS_TPM2
+
+config DRIVER_TPM_SPI_BUS
+	depends on DRAGONEGG_USE_SPI_TPM
+	default 0x1
+
+config GBB_HWID
+	string
+	depends on CHROMEOS
+	default "DRAGONEGG TEST 1394"
+
+config MAINBOARD_DIR
+	string
+	default "google/dragonegg"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Dragonegg"
+
+config MAINBOARD_VENDOR
+	string
+	default "Google"
+
+config MAINBOARD_FAMILY
+	string
+	default "Google_Dragonegg"
+
+config MAX_CPUS
+	int
+	default 8
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 48 # GPE0_DW1_16 (GPP_D16)
+
+config VARIANT_DIR
+	string
+	default "dragonegg" if BOARD_GOOGLE_DRAGONEGG
+
+config UART_FOR_CONSOLE
+	int
+	default 0
+
+config VBOOT
+	select VBOOT_LID_SWITCH
+	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select HAS_RECOVERY_MRC_CACHE
+	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+
+endif # BOARD_GOOGLE_BASEBOARD_DRAGONEGG

src/mainboard/google/dragonegg/Kconfig.name

@@ -0,0 +1,5 @@
+comment "DragonEgg"
+
+config BOARD_GOOGLE_DRAGONEGG
+	bool "->  DragonEgg"
+	select BOARD_GOOGLE_BASEBOARD_DRAGONEGG

src/mainboard/google/dragonegg/Makefile.inc

@@ -0,0 +1,37 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += bootblock.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += romstage_fsp_params.c
+
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-y += mainboard.c
+ramstage-y += ramstage.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+
+subdirs-y += spd

src/mainboard/google/dragonegg/acpi_tables.c

@@ -0,0 +1,3 @@
+/*
+ * Blank file required by build system assumptions of this file being present.
+ */

src/mainboard/google/dragonegg/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: google
+Board name: Dragon Egg
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/google/dragonegg/bootblock.c

@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+void bootblock_mainboard_init(void)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_early_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}

src/mainboard/google/dragonegg/chromeos.c

@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <rules.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include <variant/gpio.h>
+
+#if ENV_RAMSTAGE
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+		{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
+		 "EC in RW"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+#endif /* ENV_RAMSTAGE */
+
+int get_write_protect_state(void)
+{
+	/* Read PCH_WP GPIO. */
+	return gpio_get(GPIO_PCH_WP);
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	const struct cros_gpio *gpios;
+	size_t num;
+
+	gpios = variant_cros_gpios(&num);
+	chromeos_acpi_gpio_generate(gpios, num);
+}

src/mainboard/google/dragonegg/chromeos.fmd

@@ -0,0 +1,42 @@
+FLASH@0xfe000000 0x2000000 {
+	SI_ALL@0x0 0x3F0000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000 0x36F000
+	}
+	SI_BIOS@0x1400000 0xC00000 {
+		RW_SECTION_A@0x0 0x2d0000 {
+			VBLOCK_A@0x0 0x10000
+			FW_MAIN_A(CBFS)@0x10000 0x2bffc0
+			RW_FWID_A@0x2cffc0 0x40
+		}
+		RW_SECTION_B@0x2d0000 0x2d0000 {
+			VBLOCK_B@0x0 0x10000
+			FW_MAIN_B(CBFS)@0x10000 0x2bffc0
+			RW_FWID_B@0x2cffc0 0x40
+		}
+		RW_MISC@0x5a0000 0x30000 {
+			UNIFIED_MRC_CACHE@0x0 0x20000 {
+				RECOVERY_MRC_CACHE@0x0 0x10000
+				RW_MRC_CACHE@0x10000 0x10000
+			}
+			RW_ELOG@0x20000 0x4000
+			RW_SHARED@0x24000 0x4000 {
+				SHARED_DATA@0x0 0x2000
+				VBLOCK_DEV@0x2000 0x2000
+			}
+			RW_VPD@0x28000 0x2000
+			RW_NVRAM@0x2a000 0x6000
+		}
+		RW_LEGACY(CBFS)@0x5d0000 0x200000
+		WP_RO@0x7d0000 0x430000 {
+			RO_VPD@0x0 0x4000
+			RO_SECTION@0x4000 0x42c000 {
+				FMAP@0x0 0x800
+				RO_FRID@0x800 0x40
+				RO_FRID_PAD@0x840 0x7c0
+				GBB@0x1000 0xef000
+				COREBOOT(CBFS)@0xf0000 0x33c000
+			}
+		}
+	}
+}

src/mainboard/google/dragonegg/dsdt.asl

@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include "variant/ec.h"
+#include "variant/gpio.h"
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include <soc/intel/icelake/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <soc/intel/icelake/acpi/globalnvs.asl>
+
+	// CPU
+	#include <soc/intel/icelake/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/icelake/acpi/northbridge.asl>
+			#include <soc/intel/icelake/acpi/southbridge.asl>
+		}
+	}
+
+#if IS_ENABLED(CONFIG_CHROMEOS)
+	// Chrome OS specific
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+#endif
+
+	// Chipset specific sleep states
+	#include <soc/intel/icelake/acpi/sleepstates.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+}

src/mainboard/google/dragonegg/ec.c

@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <ec/google/chromeec/ec.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void)
+{
+	const struct google_chromeec_event_info info = {
+		.log_events = MAINBOARD_EC_LOG_EVENTS,
+		.sci_events = MAINBOARD_EC_SCI_EVENTS,
+		.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+	};
+
+	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}