mb/bytedance: Add 2 SPR sockets server board bd_egs

Bytedance bd_egs is a dual socket MB with Intel Sapphire Rapids
Scalable Processor chipset.

It's utilising:
- 2 SPR sockets
- Max 32 DIMMs
- 33x CPU PCIe slots
- AST2600 for VGA and BMC remote management

Test:
  The board boots to Linux 5.10 with all 192 cores available.
  All PCIe devices and DIMMS are working.

  # sudo dmesg --level alert,crit,err,warn
  [ 46.636896] netlink: 'consul': attribute type 1 has an invalid length.

Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d
Co-authored-by: Jinfeng Li <lijinfeng01@ieisystem.com>
Co-authored-by: Long Cao <caolong01@inspur.com>
Co-authored-by: Hao Wang <wanghao11@inspur.com>
Co-authored-by: Chenyu Lan <lanchenyu@inspur.com>
Co-authored-by: Lay Kong <lay.kong@intel.com>
Co-authored-by: Kehong Chen <kehong.chen@intel.com>
Co-authored-by: Ziang Wang <ziang.wang@intel.com>
Co-authored-by: Dong Wei <weidong.wd@bytedance.com>
Co-authored-by: Chenchen Li <lichenchen.carl@bytedance.com>
Signed-off-by: Yiwei Tang <tangyiwei.2022@bytedance.com>
Reviewed-by: Haitao Nie <niehaitao@bytedance.com>
Reviewed-by: Shijian Ge <geshijian@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/bytedance/Kconfig

@@ -0,0 +1,15 @@
+if VENDOR_BYTEDANCE
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/bytedance/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/bytedance/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "ByteDance"
+
+endif # VENDOR_BYTEDANCE

src/mainboard/bytedance/Kconfig.name

@@ -0,0 +1,2 @@
+config VENDOR_BYTEDANCE
+	bool "ByteDance"

src/mainboard/bytedance/bd_egs/Kconfig

@@ -0,0 +1,31 @@
+if BOARD_BYTEDANCE_BD_EGS
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_65536
+	select MAINBOARD_USES_FSP2_0
+	select SOC_INTEL_SAPPHIRERAPIDS_SP
+	select SUPERIO_ASPEED_AST2400
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select IPMI_KCS
+	select MEMORY_MAPPED_TPM
+	select MAINBOARD_HAS_TPM2
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
+
+config MAINBOARD_DIR
+	default "bytedance/bd_egs"
+
+config MAINBOARD_PART_NUMBER
+	default "ByteDance bd_egs"
+
+config MAINBOARD_FAMILY
+	default "Intel Eagle Stream Server"
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config MAX_SOCKET
+	default 2
+
+endif

src/mainboard/bytedance/bd_egs/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_BYTEDANCE_BD_EGS
+	bool "ByteDance bd_egs"

src/mainboard/bytedance/bd_egs/Makefile.inc

@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c gpio.c
+romstage-y += romstage.c
+ramstage-y += ramstage.c gpio.c
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include

src/mainboard/bytedance/bd_egs/acpi/platform.asl

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+/* Port 80 POST */
+OperationRegion (DBG0, SystemIO, 0x80, 0x02)
+Field (DBG0, ByteAcc, Lock, Preserve)
+{
+	IO80, 8,
+	IO81, 8
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Return (Package (){ 0, 0 })
+}

src/mainboard/bytedance/bd_egs/board.fmd

@@ -0,0 +1,13 @@
+FLASH@0xfc000000 64M {
+	SI_ALL@0x0 0x03000000 {
+		SI_DESC@0x0 0x1000
+		SI_GBE@0x1000 0x2000
+		SI_ME@0x3000 0x2fed000
+		SI_PT@0x2ff0000 0x10000
+	}
+	RW_MRC_CACHE@0x3000000 0x18000
+	FMAP 0x1000
+	RW_VPD(PRESERVE) 0x4000
+	RO_VPD(PRESERVE) 0x4000
+	COREBOOT(CBFS)
+}

src/mainboard/bytedance/bd_egs/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: ByteDance
+Board name: bd_egs
+Category: eval
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y

src/mainboard/bytedance/bd_egs/bootblock.c

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+#include <soc/gpio.h>
+#include "gpio.h"
+
+#define ASPEED_SIO_PORT 0x2E
+#define PCR_DMI_LPCIOD  0x2770
+#define PCR_DMI_LPCIOE  0x2774
+
+void bootblock_mainboard_early_init(void)
+{
+	/*
+	 * Set up decoding windows on PCH over PCR. The CPU uses two of AST2600 SIO ports,
+	 * one is connected to debug header (SUART1) and another is used as SOL (SUART2).
+	 * For bd_egs, only SUART1 is used.
+	 */
+	uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE);
+	uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN);
+
+	/* Open IO windows: 0x3f8 for com1 and 02f8 for com2 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
+	/* LPC I/O enable: com1 and com2 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
+
+	/* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
+
+	const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
+	aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+
+	const struct pad_config *pads;
+	size_t pads_num;
+	pads = get_gpio_table(&pads_num);
+	gpio_configure_pads(pads, pads_num);
+}

src/mainboard/bytedance/bd_egs/devicetree.cb

@@ -0,0 +1,34 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/spr
+	register "turbo_ratio_limit" = "0x181819191e242424"
+	register "turbo_ratio_limit_cores" = "0x3836322e2a1c1a18"
+
+	device domain 0 on
+		device pci 1f.0 on         # Intel device 1b81: PCH eSPI controller
+			chip superio/common
+				device pnp 2e.0 on
+					chip superio/aspeed/ast2400
+						register "use_espi" = "1"
+						device pnp 2e.2 on      # SUART1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.3 on      # SUART2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+					end
+				end
+			end
+			chip drivers/ipmi # BMC KCS
+				device pnp ca2.0 on end
+				register "bmc_i2c_address" = "0x20"
+				register "bmc_boot_timeout" = "60"
+			end
+			chip drivers/pc80/tpm # TPM
+				device pnp 0c31.0 on end
+			end
+		end
+	end
+end

src/mainboard/bytedance/bd_egs/dsdt.asl

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <acpi/dsdt_top.asl>
+
+	#include "acpi/platform.asl"
+
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	#include <soc/intel/xeon_sp/spr/acpi/uncore.asl>
+
+	Scope (\_SB.PC00)
+	{
+		#include <soc/intel/xeon_sp/spr/acpi/pch.asl>
+	}
+}