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aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
Both SMM_ASEG and SMM_TSEG choices work. There is periodic TCO timeout occurring. At least with DEBUG_SMI kernel reports low memory corruption. Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@@ -4,4 +4,3 @@ config CPU_INTEL_MODEL_F2X | |
select SUPPORT_CPU_UCODE_IN_CBFS | ||
select CPU_INTEL_COMMON | ||
select SSE2 | ||
select NO_SMM |
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@@ -1,5 +1,6 @@ | ||
subdirs-y += ../common | ||
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ramstage-y += model_f2x_init.c | ||
ramstage-y += mp_init.c | ||
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cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*) |
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@@ -0,0 +1,105 @@ | ||
/* SPDX-License-Identifier: GPL-2.0-only */ | ||
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#include <console/console.h> | ||
#include <cpu/intel/microcode.h> | ||
#include <cpu/intel/smm_reloc.h> | ||
#include <cpu/intel/common/common.h> | ||
#include <cpu/x86/legacy_save_state.h> | ||
#include <cpu/x86/mtrr.h> | ||
#include <cpu/x86/mp.h> | ||
#include <device/device.h> | ||
#include <device/pci_ops.h> | ||
#include <types.h> | ||
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/* Parallel MP initialization support. */ | ||
static void pre_mp_init(void) | ||
{ | ||
const void *patch = intel_microcode_find(); | ||
intel_microcode_load_unlocked(patch); | ||
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/* Setup MTRRs based on physical address size. */ | ||
x86_setup_mtrrs_with_detect(); | ||
x86_mtrr_check(); | ||
} | ||
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static int get_cpu_count(void) | ||
{ | ||
return CONFIG_MAX_CPUS; | ||
} | ||
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static void get_microcode_info(const void **microcode, int *parallel) | ||
{ | ||
*microcode = intel_microcode_find(); | ||
*parallel = !intel_ht_supported(); | ||
} | ||
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static void pre_mp_smm_init(void) | ||
{ | ||
/* Clear the SMM state in the southbridge. */ | ||
smm_southbridge_clear_state(); | ||
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/* | ||
* Run the relocation handler for on the BSP to check and set up | ||
* parallel SMM relocation. | ||
*/ | ||
smm_initiate_relocation(); | ||
} | ||
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static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, | ||
size_t *smm_save_state_size) | ||
{ | ||
printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); | ||
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smm_open(); | ||
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smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); | ||
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*smm_save_state_size = sizeof(legacy_smm_state_save_area_t); | ||
printk(BIOS_DEBUG, "Save state size: 0x%zx bytes\n", *smm_save_state_size); | ||
} | ||
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/* | ||
* The relocation work is actually performed in SMM context, but the code | ||
* resides in the ramstage module. This occurs by trampolining from the default | ||
* SMRAM entry point to here. | ||
*/ | ||
static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) | ||
{ | ||
legacy_smm_state_save_area_t *save_state; | ||
u32 smbase = staggered_smbase; | ||
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save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); | ||
save_state->smbase = smbase; | ||
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printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); | ||
printk(BIOS_DEBUG, "SMM revision: 0x%08x\n", save_state->smm_revision); | ||
printk(BIOS_DEBUG, "New SMBASE=0x%08x\n", smbase); | ||
} | ||
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static void post_mp_init(void) | ||
{ | ||
smm_close(); | ||
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/* Now that all APs have been relocated as well as the BSP let SMIs start flowing. */ | ||
global_smi_enable(); | ||
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/* Lock down the SMRAM space. */ | ||
smm_lock(); | ||
} | ||
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static const struct mp_ops mp_ops = { | ||
.pre_mp_init = pre_mp_init, | ||
.get_cpu_count = get_cpu_count, | ||
.get_smm_info = get_smm_info, | ||
.get_microcode_info = get_microcode_info, | ||
.pre_mp_smm_init = pre_mp_smm_init, | ||
/* .per_cpu_smm_trigger = smm_initiate_relocation, using default */ | ||
.relocation_handler = relocation_handler, | ||
.post_mp_init = post_mp_init, | ||
}; | ||
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void mp_init_cpus(struct bus *cpu_bus) | ||
{ | ||
/* TODO: Handle mp_init_with_smm failure? */ | ||
mp_init_with_smm(cpu_bus, &mp_ops); | ||
} |
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@@ -15,4 +15,6 @@ ramstage-y += lpc.c | |
ramstage-y += usb.c | ||
ramstage-y += usb2.c | ||
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smm-y += smihandler.c | ||
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endif |
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