soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel

Kernel pinctrl driver changed for Tiger Lake and went to old scheme. Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/ third_party/kernel/+/2116670 BUG=b:151683980 BRANCH=none TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl verify INTC34C5:00 listing all the pins. Cq-Depend:chromium:2116670 Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39801 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot · May 6, 2020 · 56e3df4 · 56e3df4
1 parent e685107
commit 56e3df4
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Showing 8 changed files with 57 additions and 97 deletions.
diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c
@@ -407,8 +407,8 @@ const struct pad_config *__weak variant_base_gpio_table(size_t *num)
 }
 
 static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_NAME),
-	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_NAME),
+	CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 };
 
 const struct cros_gpio *__weak variant_cros_gpios(size_t *num)

diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c
@@ -459,8 +459,8 @@ const struct pad_config *__weak variant_early_gpio_table(size_t *num)
 }
 
 static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM1_NAME),
-	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 };
 
 const struct cros_gpio *__weak variant_cros_gpios(size_t *num)

diff --git a/src/mainboard/google/volteer/variants/ripto/gpio.c b/src/mainboard/google/volteer/variants/ripto/gpio.c
@@ -444,8 +444,8 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 }
 
 static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
-	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 };
 
 const struct cros_gpio *variant_cros_gpios(size_t *num)

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
@@ -105,7 +105,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 }
 
 static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 };
 
 const struct cros_gpio *variant_cros_gpios(size_t *num)

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
@@ -102,7 +102,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 }
 
 static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 };
 
 const struct cros_gpio *variant_cros_gpios(size_t *num)

diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl
@@ -1,103 +1,57 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
+#include <intelblocks/gpio.h>
 #include <soc/gpio_defs.h>
+#include <soc/intel/common/acpi/gpio.asl>
 #include <soc/irq.h>
 #include <soc/pcr_ids.h>
-#include <intelblocks/gpio.h>
-#include <soc/intel/common/acpi/gpio.asl>
 #include "gpio_op.asl"
 
-Device (GCM0)
+Device (GPIO)
 {
-	Name (_HID, CROS_GPIO_NAME)
+	Name (_HID, "INT34C5")
 	Name (_UID, 0)
-	Name (_DDN, "GPIO Controller Community 0")
+	Name (_DDN, "GPIO Controller")
 
 	Name (RBUF, ResourceTemplate()
 	{
-		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0)
+		Memory32Fixed (ReadWrite, 0, 0, COM0)
+		Memory32Fixed (ReadWrite, 0, 0, COM1)
+		Memory32Fixed (ReadWrite, 0, 0, COM4)
+		Memory32Fixed (ReadWrite, 0, 0, COM5)
 		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
 			{ GPIO_IRQ14 }
 	})
 	Method (_CRS, 0, NotSerialized)
 	{
+		/* GPIO Community 0 */
 		CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+		CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
 		BAS0 = ^^PCRB (PID_GPIOCOM0)
-		Return (^RBUF)
-	}
-	Method (_STA)
-	{
-		Return (0xF)
-	}
-}
+		LEN0 = GPIO_BASE_SIZE
 
-Device (GCM1)
-{
-	Name (_HID, CROS_GPIO_NAME)
-	Name (_UID, 1)
-	Name (_DDN, "GPIO Controller Community 1")
-
-	Name (RBUF, ResourceTemplate()
-	{
-		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
-			{ GPIO_IRQ14 }
-	})
-	Method (_CRS, 0, NotSerialized)
-	{
+		/* GPIO Community 1 */
 		CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+		CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
 		BAS1 = ^^PCRB (PID_GPIOCOM1)
-		Return (^RBUF)
-	}
-	Method (_STA)
-	{
-		Return (0xF)
-	}
-}
+		LEN1 = GPIO_BASE_SIZE
 
-Device (GCM4)
-{
-	Name (_HID, CROS_GPIO_NAME)
-	Name (_UID, 4)
-	Name (_DDN, "GPIO Controller Community 4")
-
-	Name (RBUF, ResourceTemplate()
-	{
-		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
-			{ GPIO_IRQ14 }
-	})
-	Method (_CRS, 0, NotSerialized)
-	{
+		/* GPIO Community 4 */
 		CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+		CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
 		BAS4 = ^^PCRB (PID_GPIOCOM4)
-		Return (^RBUF)
-	}
-	Method (_STA)
-	{
-		Return (0xF)
-	}
-}
-
-Device (GCM5)
-{
-	Name (_HID, CROS_GPIO_NAME)
-	Name (_UID, 5)
-	Name (_DDN, "GPIO Controller Community 5")
+		LEN4 = GPIO_BASE_SIZE
 
-	Name (RBUF, ResourceTemplate()
-	{
-		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
-		{ GPIO_IRQ14 }
-	})
-	Method (_CRS, 0, NotSerialized)
-	{
+		/* GPIO Community 5 */
 		CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
+		CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
 		BAS5 = ^^PCRB (PID_GPIOCOM5)
-		Return (^RBUF)
+		LEN5 = GPIO_BASE_SIZE
+
+		Return (RBUF)
 	}
-	Method (_STA)
+
+	Method (_STA, 0, NotSerialized)
 	{
 		Return (0xF)
 	}

diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c
@@ -37,21 +37,30 @@ static const struct reset_mapping rst_map_com2[] = {
 };
 
 /*
- * This layout matches the Linux kernel pinctrl map for TGL-LP at:
+ * The GPIO pinctrl driver for Tiger Lake on Linux expects 32 GPIOs per pad
+ * group, regardless of whether or not there is a physical pad for each
+ * exposed GPIO number.
+ *
+ * This results in the OS having a sparse GPIO map, and devices that need
+ * to export an ACPI GPIO must use the OS expected number.
+ *
+ * Not all pins are usable as GPIO and those groups do not have a pad base.
+ *
+ * This layout matches the Linux kernel pinctrl map for TGL at:
  * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c
  */
 static const struct pad_group tgl_community0_groups[] = {
-	INTEL_GPP(GPP_B0, GPP_B0, GPP_B25),				/* GPP_B */
-	INTEL_GPP(GPP_B0, GPP_T0, GPP_T15),				/* GPP_T */
-	INTEL_GPP(GPP_B0, GPP_A0, GPP_A24),				/* GPP_A */
+	INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0),			/* GPP_B */
+	INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32),			/* GPP_T */
+	INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_A24, 64),			/* GPP_A */
 };
 
 static const struct pad_group tgl_community1_groups[] = {
-	INTEL_GPP(GPP_S0, GPP_S0, GPP_S7),				/* GPP_S */
-	INTEL_GPP(GPP_S0, GPP_H0, GPP_H23),				/* GPP_H */
-	INTEL_GPP(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK),		/* GPP_D */
-	INTEL_GPP(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK),		/* GPP_U */
-	INTEL_GPP(GPP_S0, CNV_BTEN, vI2S2_RXD),				/* GPP_VGPIO */
+	INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96),			/* GPP_S */
+	INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128),			/* GPP_H */
+	INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160),	/* GPP_D */
+	INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 192),	/* GPP_U */
+	INTEL_GPP_BASE(GPP_S0, CNV_BTEN, vI2S2_RXD, 224),		/* GPP_VGPIO */
 };
 
 /* This community is not visible to the OS */
@@ -60,15 +69,15 @@ static const struct pad_group tgl_community2_groups[] = {
 };
 
 static const struct pad_group tgl_community4_groups[] = {
-	INTEL_GPP(GPP_C0, GPP_C0, GPP_C23),				/* GPP_C */
-	INTEL_GPP(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK),			/* GPP_F */
+	INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256),			/* GPP_C */
+	INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288),		/* GPP_F */
 	INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB),			/* GPP_HVCMOS */
-	INTEL_GPP(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK),			/* GPP_E */
+	INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320),		/* GPP_E */
 	INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE),			/* GPP_JTAG */
 };
 
 static const struct pad_group tgl_community5_groups[] = {
-	INTEL_GPP(GPP_R0, GPP_R0, GPP_R7),				/* GPP_R */
+	INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352),			/* GPP_R */
 	INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK),		/* GPP_SPI */
 };
 

diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h
@@ -7,10 +7,7 @@
 #include <soc/gpio_defs.h>
 #include <intelblocks/gpio.h>
 
-#define CROS_GPIO_NAME		"INT34C5"
-#define CROS_GPIO_COMM0_NAME    "INT34C5:00"
-#define CROS_GPIO_COMM1_NAME    "INT34C5:01"
-#define CROS_GPIO_COMM4_NAME    "INT34C5:02"
-#define CROS_GPIO_COMM5_NAME    "INT34C5:03"
+
+#define CROS_GPIO_DEVICE_NAME	"INT34C5:00"
 
 #endif