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mb/system76/cml-u: Convert lemp9 to a variant
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Change-Id: I13777cf6f663ca8c52a059a60cfcdfe6ecc5b9ae
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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@crawfxrd @felixheld
crawfxrd authored and felixheld committed Dec 2, 2022
1 parent 1ef3779 commit 5b7b04c
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Showing 31 changed files with 483 additions and 552 deletions.
13 changes: 10 additions & 3 deletions src/mainboard/system76/cml-u/Kconfig
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
if BOARD_SYSTEM76_GALP4 || BOARD_SYSTEM76_DARP6
if BOARD_SYSTEM76_DARP6 || BOARD_SYSTEM76_GALP4 || BOARD_SYSTEM76_LEMP9

config BOARD_SPECIFIC_OPTIONS
def_bool y
Expand All @@ -10,13 +10,15 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select HAVE_SPD_IN_CBFS if BOARD_SYSTEM76_LEMP9
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MEMORY_MAPPED_TPM
select MAINBOARD_HAS_TPM2
select NO_UART_ON_SUPERIO
select PCIEXP_HOTPLUG
select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G # Fix running out of MTRRs
select PCIEXP_HOTPLUG if BOARD_SYSTEM76_DARP6 || BOARD_SYSTEM76_GALP4
# Fix running out of MTRRs
select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G if BOARD_SYSTEM76_DARP6 || BOARD_SYSTEM76_GALP4
select SOC_INTEL_COMETLAKE_1
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SPD_READ_BY_WORD
Expand All @@ -29,23 +31,28 @@ config MAINBOARD_DIR
config VARIANT_DIR
default "galp4" if BOARD_SYSTEM76_GALP4
default "darp6" if BOARD_SYSTEM76_DARP6
default "lemp9" if BOARD_SYSTEM76_LEMP9

config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"

config MAINBOARD_PART_NUMBER
default "galp4" if BOARD_SYSTEM76_GALP4
default "darp6" if BOARD_SYSTEM76_DARP6
default "lemp9" if BOARD_SYSTEM76_LEMP9

config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Galago Pro" if BOARD_SYSTEM76_GALP4
default "Darter Pro" if BOARD_SYSTEM76_DARP6
default "Lemur Pro" if BOARD_SYSTEM76_LEMP9

config MAINBOARD_VERSION
default "galp4" if BOARD_SYSTEM76_GALP4
default "darp6" if BOARD_SYSTEM76_DARP6
default "lemp9" if BOARD_SYSTEM76_LEMP9

config CBFS_SIZE
default 0xc00000 if BOARD_SYSTEM76_LEMP9
default 0xA00000

config CONSOLE_POST
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3 changes: 3 additions & 0 deletions src/mainboard/system76/cml-u/Kconfig.name
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Expand Up @@ -3,3 +3,6 @@ config BOARD_SYSTEM76_GALP4

config BOARD_SYSTEM76_DARP6
bool "darp6"

config BOARD_SYSTEM76_LEMP9
bool "lemp9"
4 changes: 3 additions & 1 deletion src/mainboard/system76/cml-u/Makefile.inc
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Expand Up @@ -4,5 +4,7 @@ bootblock-y += bootblock.c
bootblock-y += gpio_early.c

ramstage-y += ramstage.c
ramstage-y += gpio.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

SPD_SOURCES = samsung-K4AAG165WA-BCTD
60 changes: 6 additions & 54 deletions src/mainboard/system76/cml-u/devicetree.cb
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Expand Up @@ -70,31 +70,14 @@ chip soc/intel/cannonlake
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4
register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 3
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4
register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT
end
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.3 on # CNVi wifi
chip drivers/wifi/generic
register "wake" = "PME_B0_EN_BIT"
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device pci 14.5 off end # SDCard
device pci 15.0 on end # I2C #0
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
Expand All @@ -104,52 +87,23 @@ chip soc/intel/cannonlake
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[2]" = "1"
end
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 off end # eMMC
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.0 off end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 on # PCI Express Port 5
# PCI Express Root port #5 x4, Clock 4 (TBT)
register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[4]" = "4"
register "PcieClkSrcClkReq[4]" = "4"
end
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on # PCI Express Port 9
# PCI Express Root port #9 x1, Clock 3 (LAN)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
end
device pci 1d.1 on # PCI Express Port 10
# PCI Express Root port #10 x1, Clock 2 (WLAN)
register "PcieRpEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "0"
register "PcieClkSrcUsage[2]" = "9"
register "PcieClkSrcClkReq[2]" = "2"
end
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on # PCI Express Port 13
# PCI Express Root port #13 x4, Clock 5 (NVMe)
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"
end
device pci 1d.4 off end # PCI Express Port 13
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15
device pci 1d.7 off end # PCI Express Port 16
Expand All @@ -169,8 +123,6 @@ chip soc/intel/cannonlake
device pci 1f.2 hidden end # Power Management Controller
device pci 1f.3 on # Intel HDA
register "PchHdaAudioLinkHda" = "1"
register "PchHdaAudioLinkDmic0" = "1"
register "PchHdaAudioLinkDmic1" = "1"
end
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
Expand Down
0 ...lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex → ...cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex
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File renamed without changes.
1 change: 0 additions & 1 deletion src/mainboard/system76/cml-u/gpio.c → ...oard/system76/cml-u/variants/darp6/gpio.c
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Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <mainboard/gpio.h>
#include <soc/gpe.h>
#include <soc/gpio.h>

static const struct pad_config gpio_table[] = {
Expand Down
58 changes: 56 additions & 2 deletions src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
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Original file line number Diff line number Diff line change
@@ -1,7 +1,24 @@
chip soc/intel/cannonlake
device domain 0 on
subsystemid 0x1558 0x1404 inherit
device pci 15.0 on

device pci 14.0 on # USB xHCI
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4
register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 3
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4
register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT
end
device pci 15.0 on # I2C #0
chip drivers/i2c/hid
register "generic.hid" = ""SYNA1202""
register "generic.desc" = ""Synaptics Touchpad""
Expand All @@ -10,6 +27,43 @@ chip soc/intel/cannonlake
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
end # I2C #0
end
device pci 17.0 on # SATA
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[2]" = "1"
end
device pci 1c.4 on # PCI Express Port 5
# PCI Express Root port #5 x4, Clock 4 (TBT)
register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[4]" = "4"
register "PcieClkSrcClkReq[4]" = "4"
end
device pci 1d.0 on # PCI Express Port 9
# PCI Express Root port #9 x1, Clock 3 (LAN)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
end
device pci 1d.1 on # PCI Express Port 10
# PCI Express Root port #10 x1, Clock 2 (WLAN)
register "PcieRpEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "0"
register "PcieClkSrcUsage[2]" = "9"
register "PcieClkSrcClkReq[2]" = "2"
end
device pci 1d.4 on # PCI Express Port 13
# PCI Express Root port #13 x4, Clock 5 (NVMe)
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"
end
device pci 1f.3 on # Intel HDA
register "PchHdaAudioLinkDmic0" = "1"
register "PchHdaAudioLinkDmic1" = "1"
end
end
end
4 changes: 2 additions & 2 deletions src/mainboard/system76/cml-u/romstage.c → .../system76/cml-u/variants/darp6/romstage.c
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Original file line number Diff line number Diff line change
Expand Up @@ -6,11 +6,11 @@
static const struct cnl_mb_cfg memcfg = {
.spd[0] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa0},
.spd_spec = { .spd_smbus_address = 0xa0 },
},
.spd[2] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa4},
.spd_spec = { .spd_smbus_address = 0xa4 },
},
.rcomp_resistor = { 121, 81, 100 },
.rcomp_targets = { 100, 40, 20, 20, 26 },
Expand Down

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