Skip to content

Commit

Permalink
SNB+MRC boards: Migrate MRC settings to devicetree
Browse files Browse the repository at this point in the history 
For Sandy Bridge boards with MRC raminit support, migrate as much
MRC settings to devicetree as possible, to stop mainboard code from
needlessly overwriting entire PEI data structure, so they will not
interfere with upcoming transition to one standard Haswell way of
providing SPD info to northbridge.

Some exceptions allowed are described below and in code comments.

SPD-related items are kept out of devicetree for now. They will be
migrated (with a different representation) with the Haswell SPD
transition.

google/{butterfly,link,parrot,stout} have max DDR3 frequency set in
pei_data to 1600 (2*800), but in devicetree to 666. The reason for the
difference seems to be problems with native raminit code. These are
converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an
added "fix me" tag. asus/p8x7x-series also needs the same treatment,
based on testing various memory on p8z77-m hardware.

TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested.

Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
  • Loading branch information
@felixheld
Keith Hui authored and felixheld committed Oct 25, 2023
1 parent b7cbb7c commit 7039edd
Show file tree
Hide file tree
Showing 29 changed files with 333 additions and 609 deletions.
18 changes: 18 additions & 0 deletions src/mainboard/asus/p8x7x-series/devicetree.cb
View file
@@ -1,6 +1,24 @@
## SPDX-License-Identifier: GPL-2.0-only

chip northbridge/intel/sandybridge
# All MRC-capable boards in family (P8Z77-M[ PRO]) lists supported
# DIMMs down to 1.25v
register "ddr3lv_support" = "1"
# FIXME: Nothing can run native at 800MHz on p8z77-m, others may have same problem
register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"

register "usb_port_config" = "{
{1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
{1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
{1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080}
}"
# 4 bit switch mask. 0=not switchable, 1=switchable
# Means once it's loaded the OS, it can swap ports
# from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
register "usb3.hs_port_switch_mask" = "0xf"
# (The other 3 usb3.* settings can be set from nvram options, and so are set
# from runtime code)

device domain 0 on
device ref host_bridge on end # Host bridge
device ref peg10 on end # PCIEX16_1
Expand Down
26 changes: 1 addition & 25 deletions src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
View file
Expand Up @@ -52,34 +52,10 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)

void mainboard_fill_pei_data(struct pei_data *pei)
{
uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */
uint16_t usbcfg[16][3] = {
/* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
{1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
{1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
{1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080}
};
const uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */

memcpy(pei->spd_addresses, &spdaddr, sizeof(spdaddr));

pei->gbe_enable = 0; /* Board uses no Intel GbE but a RTL8111F */
pei->max_ddr3_freq = 1600; /* 1333=Sandy; 1600=Ivy */

memcpy(pei->usb_port_config, &usbcfg, sizeof(usbcfg));

/* ASUS P8Z77-M manual lists some supported DIMMs down to 1.25v */
pei->ddr3lv_support = 1;
/*
* PCIe 3.0 support. As we use Ivy Bridge, let's enable it,
* but might cause some system instability!
*/
pei->pcie_init = 1;
/*
* 4 bit switch mask. 0=not switchable, 1=switchable
* Means once it's loaded the OS, it can swap ports
* from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
*/
pei->usb3.hs_port_switch_mask = 0xf;
/*
* USB 3 mode settings.
* These are obtained from option table then bit masked to keep within range.
Expand Down
5 changes: 5 additions & 0 deletions src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
View file
@@ -1,6 +1,11 @@
## SPDX-License-Identifier: GPL-2.0-only

chip northbridge/intel/sandybridge
register "usb_port_config" = "{
{1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
{1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
{1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080}
}"
device domain 0 on
subsystemid 0x1043 0x84ca inherit
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
Expand Down
89 changes: 7 additions & 82 deletions src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
View file
Expand Up @@ -58,6 +58,10 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)

void mainboard_fill_pei_data(struct pei_data *pei_data)
{
const uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */

memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));

/*
* USB3 mode:
* 0 = Disable: work always as USB 2.0(ehci)
Expand All @@ -66,88 +70,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
* 3 = Smart Auto : same than Auto, but if OS loads USB3 driver
* and reboots, it will keep the USB3.0 speed
*/
unsigned int usb3_mode = get_uint_option("usb3_mode", 1);
usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */

pei_data->usb3.mode = get_uint_option("usb3_mode", 1) & 0x3;
/* Load USB3 pre-OS xHCI driver */
unsigned int usb3_drv = get_uint_option("usb3_drv", 1);
usb3_drv &= 0x1; /* ensure it's 0/1 only */

pei_data->usb3.preboot_support = get_uint_option("usb3_drv", 1) & 0x1;
/* Use USB3 xHCI streams */
unsigned int usb3_streams = get_uint_option("usb3_streams", 1);
usb3_streams &= 0x1; /* ensure it's 0/1 only */

struct pei_data pd = {
.pei_version = PEI_VERSION,
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
.system_type = 1, /* 0=Mobile, 1=Desktop/Server */
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */
.gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */
.max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */
.usb_port_config = {
/* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
{ 1, 0, 0x0080 }, /* USB3 front internal header */
{ 1, 0, 0x0080 }, /* USB3 front internal header */
{ 1, 1, 0x0080 }, /* USB3 ETH top connector */
{ 1, 1, 0x0080 }, /* USB3 ETH bottom connector */
{ 1, 2, 0x0080 }, /* USB2 PS2 top connector */
{ 1, 2, 0x0080 }, /* USB2 PS2 bottom connector */
{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
{ 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
{ 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
{ 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */
{ 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */
{ 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */
{ 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */
},
.usb3 = {
/* 0=Disable; 1=Enable (start at USB3 speed)
* 2=Auto (start as USB2 speed until OS loads)
* 3=Smart Auto (like Auto but keep speed on reboot)
*/
usb3_mode,
/* 4 bit switch mask. 0=not switchable, 1=switchable
* Means once it's loaded the OS, it can swap ports
* from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
*/
0xf,
usb3_drv, /* 1=Load xHCI pre-OS drv */
/* 0=Don't use xHCI streams for better compatibility
* 1=use xHCI streams for better speed
*/
usb3_streams
},
/* ASUS P8Z77-M PRO manual says 1.35v DIMMs are supported */
.ddr3lv_support = 1,
/* PCIe 3.0 support. As we use Ivy Bridge, let's enable it,
* but might cause some system instability !
*/
.pcie_init = 1,
/* Command Rate. 0=Auto; 1=1N; 2=2N.
* Leave it always at Auto for compatibility & stability
*/
.nmode = 0,
/* DDR refresh rate. 0=Auto based on DRAM's temperature;
* 1=Normal rate for speed; 2=Double rate for stability
*/
.ddr_refresh_rate_config = 0
};

/* copy the data to output PEI */
*pei_data = pd;
pei_data->usb3.xhci_streams = get_uint_option("usb3_streams", 1) & 0x1;
}
5 changes: 5 additions & 0 deletions src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
View file
@@ -1,6 +1,11 @@
## SPDX-License-Identifier: GPL-2.0-only

chip northbridge/intel/sandybridge
register "usb_port_config" = "{
{1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
{1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
{1, 6, 0x0080}, {1, 5, 0x0080}, {0, 5, 0x0080}, {0, 6, 0x0080}
}"
device domain 0 on
subsystemid 0x1043 0x84ca inherit
chip southbridge/intel/bd82x6x
Expand Down
22 changes: 21 additions & 1 deletion src/mainboard/google/butterfly/devicetree.cb
View file
Expand Up @@ -18,7 +18,27 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x000001e8"
register "gpu_pch_backlight" = "0x03d00000"

register "max_mem_clock_mhz" = "666" # DDR3-1333
register "ec_present" = "1"
# FIXME: Native raminit requires reduced max clock
register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
# Force double refresh rate
register "ddr_refresh_rate_config" = "DDR_REFRESH_RATE_DOUBLE"

register "usb_port_config" = "{
{ 1, 0, 0x0040 },
{ 1, 0, 0x0040 },
{ 1, 0, 0x0040 },
{ 0, 0, 0x0000 },
{ 0, 0, 0x0000 },
{ 0, 0, 0x0000 },
{ 0, 0, 0x0000 },
{ 0, 0, 0x0000 },
{ 0, 4, 0x0000 },
{ 1, 4, 0x0080 },
{ 1, 4, 0x0040 },
{ 0, 4, 0x0000 },
{ 0, 4, 0x0000 },
{ 0, 4, 0x0000 },}"

device domain 0 on
device ref host_bridge on end # host bridge
Expand Down
46 changes: 5 additions & 41 deletions src/mainboard/google/butterfly/early_init.c
View file
Expand Up @@ -74,45 +74,9 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)

void mainboard_fill_pei_data(struct pei_data *pei_data)
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
.system_type = 0, // 0 Mobile, 1 Desktop/Server
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
.ddr3lv_support = 0,
.max_ddr3_freq = 1600,
.usb_port_config = {
/* enabled USB oc pin length */
{ 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */
{ 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */
{ 1, 0, 0x0040 }, /* P2: Camera (no OC) */
{ 0, 0, 0x0000 }, /* P3: Empty */
{ 0, 0, 0x0000 }, /* P4: Empty */
{ 0, 0, 0x0000 }, /* P5: Empty */
{ 0, 0, 0x0000 }, /* P6: Empty */
{ 0, 0, 0x0000 }, /* P7: Empty */
{ 0, 4, 0x0000 }, /* P8: Empty */
{ 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */
{ 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */
{ 0, 4, 0x0000 }, /* P11: Empty */
{ 0, 4, 0x0000 }, /* P12: Empty */
{ 0, 4, 0x0000 }, /* P13: Empty */
},
.ddr_refresh_rate_config = 2, /* Force double refresh rate */
};
*pei_data = pei_data_template;
const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00};

memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));

/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
}
21 changes: 20 additions & 1 deletion src/mainboard/google/link/devicetree.cb
View file
Expand Up @@ -17,7 +17,26 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"

register "max_mem_clock_mhz" = "666"
register "ec_present" = "1"
register "ddr3lv_support" = "1"
# FIXME: Native raminit requires reduced max clock
register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"

register "usb_port_config" = "{
{ 0, 3, 0x0000 },
{ 1, 0, 0x0040 },
{ 1, 1, 0x0040 },
{ 1, 3, 0x0040 },
{ 0, 3, 0x0000 },
{ 1, 3, 0x0040 },
{ 0, 3, 0x0000 },
{ 0, 3, 0x0000 },
{ 1, 4, 0x0040 },
{ 1, 4, 0x0040 },
{ 0, 4, 0x0000 },
{ 0, 4, 0x0000 },
{ 0, 4, 0x0000 },
{ 0, 4, 0x0000 },}"

device domain 0 on
subsystemid 0x1ae0 0xc000 inherit
Expand Down
42 changes: 2 additions & 40 deletions src/mainboard/google/link/early_init.c
View file
Expand Up @@ -83,46 +83,8 @@ static uint8_t *locate_spd(void)

void mainboard_fill_pei_data(struct pei_data *pei_data)
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
.system_type = 0, // 0 Mobile, 1 Desktop/Server
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
.ddr3lv_support = 1,
.max_ddr3_freq = 1600,
.usb_port_config = {
/* Empty and onboard Ports 0-7, set to un-used pin OC3 */
{ 0, 3, 0x0000 }, /* P0: Empty */
{ 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */
{ 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */
{ 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */
{ 0, 3, 0x0000 }, /* P4: Empty */
{ 1, 3, 0x0040 }, /* P5: WWAN (no OC) */
{ 0, 3, 0x0000 }, /* P6: Empty */
{ 0, 3, 0x0000 }, /* P7: Empty */
/* Empty and onboard Ports 8-13, set to un-used pin OC4 */
{ 1, 4, 0x0040 }, /* P8: Camera (no OC) */
{ 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */
{ 0, 4, 0x0000 }, /* P10: Empty */
{ 0, 4, 0x0000 }, /* P11: Empty */
{ 0, 4, 0x0000 }, /* P12: Empty */
{ 0, 4, 0x0000 }, /* P13: Empty */
},
};
*pei_data = pei_data_template;
/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */

/* LINK has 2 channels of memory down, so spd_data[0] and [2]
both need to be populated */
memcpy(pei_data->spd_data[0], locate_spd(),
Expand Down
20 changes: 19 additions & 1 deletion src/mainboard/google/parrot/devicetree.cb
View file
Expand Up @@ -17,7 +17,25 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x000001d4"
register "gpu_pch_backlight" = "0x03aa0000"

register "max_mem_clock_mhz" = "666"
register "ec_present" = "1"
# FIXME: Native raminit requires reduced max clock
register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"

register "usb_port_config" = "{
{ 0, 3, 0x0000 },
{ 1, 0, 0x0040 },
{ 1, 1, 0x0040 },
{ 1, 1, 0x0040 },
{ 0, 3, 0x0000 },
{ 0, 3, 0x0000 },
{ 0, 3, 0x0000 },
{ 0, 3, 0x0000 },
{ 1, 4, 0x0040 },
{ 0, 4, 0x0000 },
{ 1, 4, 0x0040 },
{ 0, 4, 0x0000 },
{ 0, 4, 0x0000 },
{ 0, 4, 0x0000 },}"

device domain 0 on
device ref host_bridge on end # host bridge
Expand Down

0 comments on commit 7039edd

Please sign in to comment.