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nb/intel/i945: Fix errors found by checkpatch.pl
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Change-Id: Ic2dd40e73d4a4c091c5ce1f49bbf9ab4d013d7af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18704
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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@ArthurHeymans
ArthurHeymans authored and Martin Roth committed Mar 22, 2017
1 parent 219daaf commit 70a8e34
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Showing 11 changed files with 452 additions and 402 deletions.
2 changes: 1 addition & 1 deletion src/northbridge/intel/i945/acpi.c
View file
Expand Up @@ -34,7 +34,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
u32 pciexbar_reg;
int max_buses;

dev = dev_find_slot(0, PCI_DEVFN(0,0));
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev)
return current;

Expand Down
2 changes: 1 addition & 1 deletion src/northbridge/intel/i945/bootblock.c
View file
Expand Up @@ -20,5 +20,5 @@ static void bootblock_northbridge_init(void)
* 4GiB.
*/
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);
}
29 changes: 12 additions & 17 deletions src/northbridge/intel/i945/debug.c
View file
Expand Up @@ -26,7 +26,7 @@ void print_pci_devices(void)
pci_devfn_t dev;
for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
dev += PCI_DEV(0, 0, 1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
Expand All @@ -36,26 +36,24 @@ void print_pci_devices(void)
}
printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
(dev >> 15) & 0x1f, (dev >> 12) & 7);
printk(BIOS_DEBUG, " [%04x:%04x]\n", id &0xffff, id >> 16);
printk(BIOS_DEBUG, " [%04x:%04x]\n", id & 0xffff, id >> 16);
}
}

void dump_pci_device(unsigned dev)
void dump_pci_device(unsigned int dev)
{
int i;

printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);

for (i = 0; i <= 255; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
}
val = pci_read_config8(dev, i);
printk(BIOS_DEBUG, " %02x", val);
if ((i & 0x0f) == 0x0f) {
if ((i & 0x0f) == 0x0f)
printk(BIOS_DEBUG, "\n");
}
}
}

Expand All @@ -64,7 +62,7 @@ void dump_pci_devices(void)
pci_devfn_t dev;
for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
dev += PCI_DEV(0, 0, 1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
Expand All @@ -78,37 +76,34 @@ void dump_pci_devices(void)

void dump_spd_registers(void)
{
unsigned device;
unsigned int device;
device = DIMM0;
while (device <= DIMM3) {
int status = 0;
int i;
printk(BIOS_DEBUG, "\ndimm %02x", device);

for (i = 0; (i < 256); i++) {
if ((i % 16) == 0) {
if ((i % 16) == 0)
printk(BIOS_DEBUG, "\n%02x: ", i);
}
status = smbus_read_byte(device, i);
if (status < 0) {
if (status < 0)
printk(BIOS_DEBUG, "bad device: %02x\n", -status);
break;
}
printk(BIOS_DEBUG, "%02x ", status);
}
device++;
printk(BIOS_DEBUG, "\n");
}
}

void dump_mem(unsigned start, unsigned end)
void dump_mem(unsigned int start, unsigned int end)
{
unsigned i;
unsigned int i;
printk(BIOS_DEBUG, "dump_mem:");
for (i = start; i < end; i++) {
if ((i & 0xf)==0) {
if ((i & 0xf) == 0)
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
}
printk(BIOS_DEBUG, "\n");
Expand Down
56 changes: 30 additions & 26 deletions src/northbridge/intel/i945/early_init.c
View file
Expand Up @@ -160,10 +160,10 @@ static void i945_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);

pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */

pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */
setup_pch_gpios(&mainboard_gpio_map);
printk(BIOS_DEBUG, " done.\n");

Expand Down Expand Up @@ -253,7 +253,7 @@ static void i945_setup_egress_port(void)
EPBAR32(EPVC1RCAP) = reg32;

if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
if ((MCHBAR32(CLKCFG) & 7) == 0){ /* 1067MHz */
if ((MCHBAR32(CLKCFG) & 7) == 0) { /* 1067MHz */
EPBAR32(EPVC1IST + 0) = 0x01380138;
EPBAR32(EPVC1IST + 4) = 0x01380138;
}
Expand All @@ -275,9 +275,8 @@ static void i945_setup_egress_port(void)
}

/* Is internal graphics enabled? */
if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
MCHBAR32(MMARB1) |= (1 << 17);
}

/* Assign Virtual Channel ID 1 to VC1 */
reg32 = EPBAR32(EPVC1RCTL);
Expand Down Expand Up @@ -305,7 +304,8 @@ static void i945_setup_egress_port(void)
printk(BIOS_DEBUG, "Loading port arbitration table ...");
/* Loop until bit 0 becomes 0 */
timeout = 0x7fffff;
while ((EPBAR16(EPVC1RSTS) & 1) && --timeout);
while ((EPBAR16(EPVC1RSTS) & 1) && --timeout)
;
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
else
Expand All @@ -317,7 +317,8 @@ static void i945_setup_egress_port(void)
printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
/* Wait for VC1 negotiation pending */
timeout = 0x7fff;
while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout);
while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout)
;
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
else
Expand Down Expand Up @@ -355,7 +356,7 @@ static void ich7_setup_dmi_rcrb(void)
pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0);

reg32 = RCBA32(V1CTL);
reg32 &= ~( (0x7f << 1) | (7 << 17) | (7 << 24) );
reg32 &= ~((0x7f << 1) | (7 << 17) | (7 << 24));
reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31);
RCBA32(V1CTL) = reg32;

Expand Down Expand Up @@ -410,7 +411,8 @@ static void i945_setup_dmi_rcrb(void)
printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
/* Wait for VC1 negotiation pending */
timeout = 0x7ffff;
while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout);
while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout)
;
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
else
Expand All @@ -436,9 +438,8 @@ static void i945_setup_dmi_rcrb(void)

DMIBAR32(DMICC) = reg32;

if (activate_aspm) {
if (activate_aspm)
DMIBAR32(DMILCTL) |= (3 << 0);
}
#endif

/* Last but not least, some additional steps */
Expand Down Expand Up @@ -510,7 +511,8 @@ static void i945_setup_dmi_rcrb(void)
/* wait for bit toggle to 0 */
printk(BIOS_DEBUG, "Waiting for DMI hardware...");
timeout = 0x7fffff;
while ((DMIBAR8(0x32) & (1 << 1)) && --timeout);
while ((DMIBAR8(0x32) & (1 << 1)) && --timeout)
;
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
else
Expand Down Expand Up @@ -576,9 +578,8 @@ static void i945_setup_pci_express_x16(void)

reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
if (!(reg16 & 0x48)) {
if (!(reg16 & 0x48))
goto disable_pciexpress_x16_link;
}
reg16 |= (1 << 4) | (1 << 0);
pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16);

Expand All @@ -591,7 +592,7 @@ static void i945_setup_pci_express_x16(void)
reg32 &= ~(1 << 8);
pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);

MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) );
MCHBAR16(UPMC1) &= ~((1 << 5) | (1 << 0));

/* Initialize PEG_CAP */
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xa2);
Expand All @@ -613,7 +614,9 @@ static void i945_setup_pci_express_x16(void)
/* Wait for training to succeed */
printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff;
while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout);
while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)
&& --timeout)
;

reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
Expand All @@ -626,7 +629,7 @@ static void i945_setup_pci_express_x16(void)

reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS);
reg32 &= ~(0xf << 1);
reg32 |=1;
reg32 |= 1;
pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32);

reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
Expand All @@ -638,7 +641,9 @@ static void i945_setup_pci_express_x16(void)

printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff;
while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout);
while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)
&& --timeout)
;

reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
Expand All @@ -659,15 +664,14 @@ static void i945_setup_pci_express_x16(void)

reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x204);
reg32 &= 0xfffffc00; /* clear [9:0] */
if (reg16 == 1) {
if (reg16 == 1)
reg32 |= 0x32b;
// TODO
/* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
} else if (reg16 == 16) {
else if (reg16 == 16)
reg32 |= 0x0f4;
// TODO
/* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
}

reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32);
Expand Down Expand Up @@ -749,11 +753,10 @@ static void i945_setup_pci_express_x16(void)
pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32);

reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
if (i945_silicon_revision() >= 2) {
if (i945_silicon_revision() >= 2)
reg32 |= (1 << 12);
} else {
else
reg32 &= ~(1 << 12);
}
pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);

reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4);
Expand All @@ -780,7 +783,7 @@ static void i945_setup_pci_express_x16(void)
}
}

if (i945_silicon_revision() <= 2 ) {
if (i945_silicon_revision() <= 2) {
/* Set voltage specific parameters */
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
reg32 &= (0xf << 4); /* Default case 1.05V */
Expand Down Expand Up @@ -813,7 +816,8 @@ static void i945_setup_pci_express_x16(void)
printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
timeout = 0x7fffff;
for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS);
(reg32 & 0x000f0000) && --timeout;);
(reg32 & 0x000f0000) && --timeout;)
;
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
else
Expand Down

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