Revert "mb/aopen/dxplplusu: Remove board"

This reverts commit eb76a45
and applies minor fixes to make it build again.

PARALLEL_MP was working prior to board removal and no
relevant SMI handlers were implemented. So NO_SMM choice
is now selected.

Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/arch/x86/smbios.c

@@ -382,6 +382,8 @@ static int get_socket_type(void)
 {
 	if (CONFIG(CPU_INTEL_SLOT_1))
 		return 0x08;
+	if (CONFIG(CPU_INTEL_SOCKET_MPGA604))
+		return 0x13;
 	if (CONFIG(CPU_INTEL_SOCKET_LGA775))
 		return 0x15;
 	if (CONFIG(XEON_SP_COMMON_BASE))

src/cpu/intel/Kconfig

@@ -10,6 +10,7 @@ source "src/cpu/intel/model_1067x/Kconfig"
 source "src/cpu/intel/model_106cx/Kconfig"
 source "src/cpu/intel/model_206ax/Kconfig"
 source "src/cpu/intel/model_2065x/Kconfig"
+source "src/cpu/intel/model_f2x/Kconfig"
 source "src/cpu/intel/model_f3x/Kconfig"
 source "src/cpu/intel/model_f4x/Kconfig"
 source "src/cpu/intel/haswell/Kconfig"
@@ -19,6 +20,7 @@ source "src/cpu/intel/socket_BGA956/Kconfig"
 source "src/cpu/intel/socket_FCBGA559/Kconfig"
 source "src/cpu/intel/socket_m/Kconfig"
 source "src/cpu/intel/socket_p/Kconfig"
+source "src/cpu/intel/socket_mPGA604/Kconfig"
 source "src/cpu/intel/socket_441/Kconfig"
 source "src/cpu/intel/socket_LGA775/Kconfig"
 # Architecture specific features

src/cpu/intel/Makefile.inc

@@ -9,6 +9,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
 subdirs-$(CONFIG_CPU_INTEL_MODEL_2065X) += model_2065x
 subdirs-$(CONFIG_CPU_INTEL_MODEL_206AX) += model_206ax
 subdirs-$(CONFIG_CPU_INTEL_HASWELL) += haswell

src/cpu/intel/model_f2x/Kconfig

@@ -0,0 +1,7 @@
+config CPU_INTEL_MODEL_F2X
+	bool
+	select ARCH_X86
+	select SUPPORT_CPU_UCODE_IN_CBFS
+	select CPU_INTEL_COMMON
+	select SSE2
+	select NO_SMM

src/cpu/intel/model_f2x/Makefile.inc

@@ -0,0 +1,5 @@
+subdirs-y += ../common
+
+ramstage-y += model_f2x_init.c
+
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*)

src/cpu/intel/model_f2x/model_f2x_init.c

@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/common/common.h>
+#include <cpu/x86/cache.h>
+
+static void model_f2x_init(struct device *cpu)
+{
+	/* Turn on caching if we haven't already */
+	enable_cache();
+};
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_f2x_init,
+};
+
+static const struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0f22 },
+	{ X86_VENDOR_INTEL, 0x0f24 },
+	{ X86_VENDOR_INTEL, 0x0f25 },
+	{ X86_VENDOR_INTEL, 0x0f26 },
+	{ X86_VENDOR_INTEL, 0x0f27 },
+	{ X86_VENDOR_INTEL, 0x0f29 },
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};
+
+/* Parallel MP initialization support. */
+static void pre_mp_init(void)
+{
+	const void *patch = intel_microcode_find();
+	intel_microcode_load_unlocked(patch);
+
+	/* Setup MTRRs based on physical address size. */
+	x86_setup_mtrrs_with_detect();
+	x86_mtrr_check();
+}
+
+static int get_cpu_count(void)
+{
+	return CONFIG_MAX_CPUS;
+}
+
+static void get_microcode_info(const void **microcode, int *parallel)
+{
+	*microcode = intel_microcode_find();
+	*parallel = !intel_ht_supported();
+}
+
+static const struct mp_ops mp_ops = {
+	.pre_mp_init = pre_mp_init,
+	.get_cpu_count = get_cpu_count,
+	.get_microcode_info = get_microcode_info,
+};
+
+void mp_init_cpus(struct bus *cpu_bus)
+{
+	mp_init_with_smm(cpu_bus, &mp_ops);
+}

src/cpu/intel/socket_mPGA604/Kconfig

@@ -0,0 +1,36 @@
+config CPU_INTEL_SOCKET_MPGA604
+	bool
+
+if CPU_INTEL_SOCKET_MPGA604
+
+config SOCKET_SPECIFIC_OPTIONS
+	def_bool y
+	select CPU_INTEL_MODEL_F2X
+	select MMX
+	select SSE
+	select UDELAY_TSC
+	select TSC_MONOTONIC_TIMER
+	select SIPI_VECTOR_IN_ROM
+	select CPU_INTEL_COMMON
+	select CPU_INTEL_COMMON_TIMEBASE
+
+# mPGA604 are usually Intel Netburst CPUs which should have SSE2
+# but the ramtest.c code on the Dell S1850 seems to choke on
+# enabling it, so disable it for now.
+config SSE2
+	bool
+	default n
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xfefc0000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x4000
+
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x2000
+
+endif # CPU_INTEL_SOCKET_MPGA604

src/cpu/intel/socket_mPGA604/Makefile.inc

@@ -0,0 +1,9 @@
+subdirs-y += ../model_f2x
+subdirs-y += ../../x86/lapic
+subdirs-y += ../microcode
+
+bootblock-y += ../car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
+
+postcar-y += ../car/p4-netburst/exit_car.S
+romstage-y += ../car/romstage.c

src/cpu/x86/Kconfig

@@ -172,7 +172,7 @@ config SMM_LAPIC_REMAP_MITIGATION
 	bool
 	default y if NORTHBRIDGE_INTEL_I945 || NORTHBRIDGE_INTEL_GM45 \
 		|| NORTHBRIDGE_INTEL_X4X || NORTHBRIDGE_INTEL_PINEVIEW \
-		|| NORTHBRIDGE_INTEL_IRONLAKE
+		|| NORTHBRIDGE_INTEL_E7505 || NORTHBRIDGE_INTEL_IRONLAKE
 	default n
 
 config X86_AMD_FIXED_MTRRS

src/mainboard/aopen/Kconfig

@@ -0,0 +1,15 @@
+if VENDOR_AOPEN
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/aopen/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/aopen/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "AOpen"
+
+endif # VENDOR_AOPEN

src/mainboard/aopen/Kconfig.name

@@ -0,0 +1,2 @@
+config VENDOR_AOPEN
+	bool "AOpen"

src/mainboard/aopen/dxplplusu/Kconfig

@@ -0,0 +1,27 @@
+if BOARD_AOPEN_DXPLPLUSU
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select CPU_INTEL_SOCKET_MPGA604
+	select NORTHBRIDGE_INTEL_E7505
+	select SOUTHBRIDGE_INTEL_I82870
+	select SOUTHBRIDGE_INTEL_I82801DX
+	select SUPERIO_SMSC_LPC47M10X
+	select HAVE_ACPI_TABLES
+	select BOARD_ROMSIZE_KB_2048
+
+config MAINBOARD_DIR
+	default "aopen/dxplplusu"
+
+config MAINBOARD_PART_NUMBER
+	default "DXPL Plus-U"
+
+config IRQ_SLOT_COUNT
+	int
+	default 12
+
+config MAX_CPUS
+	int
+	default 4
+
+endif # BOARD_AOPEN_DXPLPLUSU

src/mainboard/aopen/dxplplusu/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_AOPEN_DXPLPLUSU
+	bool "DXPL Plus-U"

src/mainboard/aopen/dxplplusu/Makefile.inc

@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c

src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl

@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (MBRS)
+{
+	Name (_HID, EisaId ("PNP0C01"))
+	Name (_UID, 0x01)
+	Name (MSBF, ResourceTemplate ()
+	{
+		/* System memory */
+		QWordMemory (ResourceProducer, PosDecode, MinFixed,
+			MaxNotFixed, Prefetchable, ReadWrite,
+			0x0, 0x100000000, 0x400000000, 0x0, 0x0, ,, _Y1C,
+			AddressRangeMemory, TypeStatic)
+
+		/* Top Of Low Memory */
+		Memory32 (ReadOnly, 0x0, 0x0, 0x1, 0x0, _Y1D)
+
+		/* 640kB who wants more? */
+		Memory32Fixed (ReadWrite, 0x0, 0xA0000, )
+
+		/* 64k BIOS bootblock */
+		Memory32Fixed (ReadOnly, 0xF0000, 0x10000,)
+
+		/* ISA memory hole 15-16 MB ? */
+		/* Memory32Fixed (ReadOnly, 0x100000, 0xF00000,) */
+		/* ISA memory hole 14-15 MB ? */
+		/* Memory32Fixed (ReadOnly, 0x100000, 0xE00000,) */
+
+		/* Local APIC */
+		Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000,)
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		CreateQWordField (MSBF, \_SB.MBRS._Y1C._MIN, MEML)
+		CreateQWordField (MSBF, \_SB.MBRS._Y1C._MAX, MEMM)
+		CreateQWordField (MSBF, \_SB.MBRS._Y1C._LEN, LELM)
+
+		And (\_SB.PCI0.RLAR, 0x03FF, Local1)
+		Local1++
+		If (Local1 > 0x40)
+		{
+			ShiftLeft (Local1, 0x1A, LELM)
+		}
+
+
+		CreateDWordField (MSBF, \_SB.MBRS._Y1D._MIN, MS00)
+		CreateDWordField (MSBF, \_SB.MBRS._Y1D._MAX, MS01)
+		CreateDWordField (MSBF, \_SB.MBRS._Y1D._LEN, MEM2)
+		And (\_SB.PCI0.TOLM, 0xF800, Local1)
+		ShiftRight (Local1, 0x04, Local1)
+		Local1--
+		If (Local1 > 0x10)
+		{
+			Local1 -= 0x0F
+			Store (ShiftLeft (Local1, 0x14), MEM2)
+			Store (0x01000000, MS00)
+			Store (MS00, MS01)
+		}
+
+		Return (MSBF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}

src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl

@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/ioapic.h>
+
+Name (PBRS, ResourceTemplate ()
+{
+	WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+		0x0000, 0x0000, 0x00FF, 0x0000, 0x0100, ,, )
+
+	/* System IO */
+	DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		0x0, 0x0, 0xffff, 0x0000, 0x10000, ,,, TypeStatic)
+	IO (Decode16, 0x0CF8, 0x0CF8, 0x08, 0x08, )
+
+	/* Video RAM */
+	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+		0x00000000, 0x000A0000, 0x000BFFFF,
+		0x00000000, 0x00020000, ,,, AddressRangeMemory, TypeStatic)
+
+	/* Video ROM */
+	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+		0x00000000, 0x000C0000, 0x000C7FFF,
+		0x00000000, 0x00008000, ,,, AddressRangeMemory, TypeStatic)
+
+	/* Option ROMs ? */
+	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+		0x00000000, 0x000C8000, 0x000DFFFF,
+		0x00000000, 0x00018000, ,,, AddressRangeMemory, TypeStatic)
+
+	/* Top Of Lowmemory to IOAPIC */
+	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+		0x00000000, 0x00000000, 0xFEBFFFFF,
+		0x00000000, IO_APIC_ADDR, ,, _Y08, AddressRangeMemory, TypeStatic)
+})
+
+
+Method (_CRS, 0, NotSerialized)
+{
+
+	/* Top Of Lowmemory to IOAPIC */
+	CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML)
+	CreateDWordField (PBRS, \_SB.PCI0._Y08._MAX, MEMH)
+	CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM)
+	And (\_SB.PCI0.TOLM, 0xF800, Local1)
+	ShiftRight (Local1, 0x04, Local1)
+	ShiftLeft (Local1, 0x14, MEML)
+	MEMH = IO_APIC_ADDR - 1
+	LENM = IO_APIC_ADDR - MEML
+
+	Return (PBRS)
+}
+
+Method (_STA, 0, NotSerialized)
+{
+	Return (0x0F)
+}