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Adds initialisation of 512MB of DDR memory on the BBB to the romstage. The parameters for the DDR peripherals are taken from U-Boot. TEST: Booted from romstage into ramstage. Also successfully managed to run the "ram_check" in lib.h. Change-Id: I692bfd913c8217a78d073d19c5344c9bb40722a8 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@@ -24,7 +24,7 @@ config MAX_CPUS | |
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config DRAM_SIZE_MB | ||
int | ||
default 256 | ||
default 512 | ||
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config UART_FOR_CONSOLE | ||
int | ||
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/* SPDX-License-Identifier: GPL-2.0-only */ | ||
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/* | ||
* Parameters to initialise the DDR3 memory on the Beaglebone Black | ||
* Taken and adapted from U-Boot. | ||
*/ | ||
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#ifndef __MAINBOARD_TI_BEAGLEBONE_DDR3_H__ | ||
#define __MAINBOARD_TI_BEAGLEBONE_DDR3_H__ | ||
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/* Micron MT41K256M16HA-125E */ | ||
#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 | ||
#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB | ||
#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA | ||
#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F | ||
#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 | ||
#define MT41K256M16HA125E_EMIF_SDREF 0xC30 | ||
#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 | ||
#define MT41K256M16HA125E_RATIO 0x80 | ||
#define MT41K256M16HA125E_INVERT_CLKOUT 0x0 | ||
#define MT41K256M16HA125E_RD_DQS 0x38 | ||
#define MT41K256M16HA125E_WR_DQS 0x44 | ||
#define MT41K256M16HA125E_PHY_WR_DATA 0x7D | ||
#define MT41K256M16HA125E_PHY_FIFO_WE 0x94 | ||
#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B | ||
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#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414 | ||
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#endif |
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