Skip to content

Commit

Permalink
AGESA: Remove heap allocations from OemCustomize.c
Browse files Browse the repository at this point in the history 
We can simply declare these structures const.

Change-Id: I637c60cc2f83e682bd5e415b674f6e27c705ac91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
  • Loading branch information
@kmalkki
kmalkki committed Sep 26, 2017
1 parent e66e390 commit 87df267
Show file tree
Hide file tree
Showing 24 changed files with 624 additions and 1,845 deletions.
153 changes: 50 additions & 103 deletions src/mainboard/amd/inagua/OemCustomize.c
View file
Expand Up @@ -15,116 +15,63 @@

#include "PlatformGnbPcieComplex.h"

#include <string.h>
#include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>


/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/

void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;

ALLOCATE_HEAP_PARAMS AllocHeapParams;

PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
},
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
}
};

PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1)
},
// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
}
};

PCIe_COMPLEX_DESCRIPTOR Brazos = {
DESCRIPTOR_TERMINATE_LIST,
static const PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
{
0,
&PortList[0],
&DdiList[0]
};

// GNB PCIe topology Porting

//
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);

AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);

BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;

AllocHeapParams.BufferPtr += sizeof(Brazos);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;

AllocHeapParams.BufferPtr += sizeof(PortList);
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;

memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
},
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
}
};

static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1)
},
// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
}
};

((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.Flags = DESCRIPTOR_TERMINATE_LIST,
.SocketId = 0,
.PciePortList = PortList,
.DdiLinkList = DdiList,
};

InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
InitEarly->GnbConfig.PsppPolicy = 0;
}

/*----------------------------------------------------------------------------------------
Expand Down
41 changes: 1 addition & 40 deletions src/mainboard/amd/olivehill/OemCustomize.c
View file
Expand Up @@ -14,13 +14,10 @@
*/

#include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>

#include <northbridge/amd/agesa/state_machine.h>


static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
Expand Down Expand Up @@ -101,52 +98,16 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.DdiLinkList = DdiList
};


void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = FALSE;
}

/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This is the stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/

void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;

ALLOCATE_HEAP_PARAMS AllocHeapParams;

/* GNB PCIe topology Porting */

/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);

AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);

PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
}

/*----------------------------------------------------------------------------------------
Expand Down
54 changes: 7 additions & 47 deletions src/mainboard/amd/parmer/OemCustomize.c
View file
Expand Up @@ -14,8 +14,6 @@
*/

#include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>

#include <northbridge/amd/agesa/state_machine.h>
Expand Down Expand Up @@ -145,54 +143,16 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->Xhci1Enable = FALSE;
}

/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.Flags = DESCRIPTOR_TERMINATE_LIST,
.SocketId = 0,
.PciePortList = PortList,
.DdiLinkList = DdiList,
};

void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;

ALLOCATE_HEAP_PARAMS AllocHeapParams;

/* GNB PCIe topology Porting */

/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
AllocHeapParams.RequestedBufferSize = sizeof(PCIe_COMPLEX_DESCRIPTOR);

AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);

PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;

LibAmdMemFill (PcieComplexListPtr,
0,
sizeof(PCIe_COMPLEX_DESCRIPTOR),
&InitEarly->StdHeader);

PcieComplexListPtr->Flags = DESCRIPTOR_TERMINATE_LIST;
PcieComplexListPtr->SocketId = 0;
PcieComplexListPtr->PciePortList = PortList;
PcieComplexListPtr->DdiLinkList = DdiList;

InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
}

/*----------------------------------------------------------------------------------------
Expand Down

0 comments on commit 87df267

Please sign in to comment.