mainboard: Add ASUS P8H61-M LX

Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with
kernel 4.9. This code is based on the output of autoport.

The file `data.vbt` matches the VBT in the latest version of the vendor
firmware (version 4601).

This board works well under coreboot. A list of what works and what
doesn't can be found in the documentation part of this commit. To
summarise: the only known issues are that S3 suspend/resume doesn't
work, and that there is no automatic fan control via the super I/O.

Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

Documentation/mainboard/asus/p8h61-m_lx.md

@@ -0,0 +1,111 @@
+# ASUS P8H61-M LX
+
+This page describes how to run coreboot on the [ASUS P8H61-M LX].
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | yes        |
++---------------------+------------+
+| Model               | W25Q32BV   |
++---------------------+------------+
+| Size                | 4 MiB      |
++---------------------+------------+
+| Package             | DIP-8      |
++---------------------+------------+
+| Write protection    | no         |
++---------------------+------------+
+| Dual BIOS feature   | no         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom]. By default, only
+the BIOS region of the flash is writable. If you wish to change any
+other region (Management Engine or flash descriptor), then an external
+programmer is required.
+
+The following command may be used to flash coreboot:
+
+```
+$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
+```
+
+The use of `--noverify-all` is required since the Management Engine
+region is not readable even by the host.
+
+## Known issues
+
+- S3 suspend/resume does not work. This is the case for both coreboot
+  and the vendor firmware, tested with Linux 4.9, Linux 4.17, and
+  OpenBSD 6.3. Interestingly, it is possible to resume from S3 with
+  Linux, but _only_ if the resume is started immediately after the
+  suspend.
+
+- There is no automatic, OS-independent fan control. This is because
+  the super I/O hardware monitor can only obtain valid CPU temperature
+  readings from the PECI agent, whose complete initialisation is not
+  publicly documented. The `coretemp` driver can still be used for
+  accurate CPU temperature readings.
+
+## Untested
+
+- PCIe graphics
+- parallel port
+- PS/2 keyboard
+- EHCI debug
+- S/PDIF audio
+
+## Working
+
+- USB
+- Gigabit Ethernet
+- integrated graphics
+- PCIe
+- SATA
+- PS/2 mouse
+- serial port
+- hardware monitor (see [Known issues](#known-issues) for caveats)
+- onboard audio
+- front panel audio
+- native raminit (2 x 2GB, DDR3-1333)
+- native graphics init (libgfxinit)
+- flashrom under the vendor firmware
+- flashrom under coreboot
+- Wake-on-LAN
+- Using `me_cleaner` (add `-S --whitelist EFFS,FCRS` if not using
+  `me_cleaner` as part of the coreboot build process).
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x                                          |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton NCT6776                                  |
++------------------+--------------------------------------------------+
+| EC               | None                                             |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+## Extra resources
+
+- [Board manual]
+- [Flash chip datasheet][W25Q32BV]
+
+[ASUS P8H61-M LX]: https://www.asus.com/Motherboards/P8H61M_LX/
+[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[Board manual]: http://dlcdnet.asus.com/pub/ASUS/mb/LGA1155/P8H61_M_LX/E6803_P8H61-M_LX.zip

Documentation/mainboard/index.md

@@ -2,6 +2,10 @@
 
 This section contains documentation about coreboot on specific mainboards.
 
+## ASUS
+
+- [P8H61-M LX](asus/p8h61-m_lx.md)
+
 ## Cavium
 
 - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)

src/mainboard/asus/p8h61-m_lx/Kconfig

@@ -0,0 +1,73 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+if BOARD_ASUS_P8H61_M_LX
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_4096
+	select CPU_INTEL_SOCKET_LGA1155
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_INT15
+	select MAINBOARD_HAS_LIBGFXINIT
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select REALTEK_8168_RESET
+	select RT8168_SET_LED_MODE
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select SUPERIO_NUVOTON_NCT6776
+	select SUPERIO_NUVOTON_NCT6776_COM_A
+	select USE_NATIVE_RAMINIT
+
+config HAVE_IFD_BIN
+	bool
+	default n
+
+config MAINBOARD_DIR
+	string
+	default asus/p8h61-m_lx
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "P8H61-M LX"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x844d
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1043
+
+config MAX_CPUS
+	int
+	default 8
+
+#
+# These ME partitions need to be whitelisted for correct system
+# operation. Example issues from removing them include: no serial output
+# and kernel warnings about loading audio codecs.
+#
+config ME_CLEANER_ARGS
+	string
+	depends on USE_ME_CLEANER
+	default "-S --whitelist EFFS,FCRS"
+
+endif

src/mainboard/asus/p8h61-m_lx/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_ASUS_P8H61_M_LX
+	bool "P8H61-M LX"

src/mainboard/asus/p8h61-m_lx/Makefile.inc

@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/asus/p8h61-m_lx/acpi/platform.asl

@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Method(_WAK, 1)
+{
+	Return (Package() { 0, 0 })
+}
+
+Method(_PTS, 1)
+{
+}

src/mainboard/asus/p8h61-m_lx/acpi/superio.asl

@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define SUPERIO_DEV		SIO0
+#define SUPERIO_PNP_BASE	0x2e
+#define NCT6776_SHOW_PP
+#define NCT6776_SHOW_SP1
+#define NCT6776_SHOW_KBC
+#define NCT6776_SHOW_HWM
+
+#undef NCT6776_SHOW_GPIO
+
+#include <superio/nuvoton/nct6776/acpi/superio.asl>

src/mainboard/asus/p8h61-m_lx/acpi_tables.c

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+}

src/mainboard/asus/p8h61-m_lx/board_info.txt

@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/P8H61M_LX/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2011

src/mainboard/asus/p8h61-m_lx/cmos.default

@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+gfx_uma_size=64M
+nmi=Enable
+power_on_after_fail=Disable
+sata_mode=AHCI