mb/starlabs/labtop: Add LabTop Mk III

Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/labtop-mk-iii-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ben McMillen <ben@starlabs.systems>
coreboot · May 28, 2022 · ab5b7b3 · ab5b7b3
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diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -180,6 +180,7 @@ The boards in this section are not real mainboards, but emulators.
 
 ## Star Labs Systems
 
+- [LabTop Mk III](starlabs/labtop_kbl.md)
 - [LabTop Mk IV](starlabs/labtop_cml.md)
 - [StarLite Mk III](starlabs/lite_glk.md)
 - [StarLite Mk IV](starlabs/lite_glkr.md)

diff --git a/Documentation/mainboard/starlabs/labtop_kbl.md b/Documentation/mainboard/starlabs/labtop_kbl.md
@@ -0,0 +1,83 @@
+# Star LabTop Mk III
+
+## Specs
+
+- CPU (full processor specs available at https://ark.intel.com)
+    - Intel i7-8550u  (Kaby Lake Refresh)
+- EC
+    - ITE IT8987E
+    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
+    - Battery
+    - Charger, using AC adapter or USB-C PD
+    - Suspend / resume
+- GPU
+    - Intel UHD Graphics 620
+    - GOP driver is recommended, VBT is provided
+    - eDP 13-inch 1920x1080 LCD
+    - HDMI video
+    - USB-C DisplayPort video
+- Memory
+    - 8GB on-board
+- Networking
+    - 8265 PCIe WiFi / Bluetooth soldered to PCBA
+- Sound
+    - Realtek ALC256
+    - Internal speakers
+    - Internal microphone
+    - Combined headphone / microphone 3.5-mm jack
+    - HDMI audio
+    - USB-C DisplayPort audio
+- Storage
+    - M.2 PCIe SSD
+    - RTS5129 MicroSD card reader
+- USB
+    - 1280x720 CCD camera
+    - USB 3.1 Gen 2 Type-C (left)
+    - USB 3.1 Gen 2 Type-A (left)
+    - USB 3.1 Gen 1 Type-A (right)
+
+## Building coreboot
+
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+
+The below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl
+make
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Vendor              | Gigadevice |
++---------------------+------------+
+| Model               | 25Q128JVSQ |
++---------------------+------------+
+| Size                | 8  MiB     |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+| External flashing   | yes        |
++---------------------+------------+
+
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.
diff --git a/src/mainboard/starlabs/labtop/Kconfig b/src/mainboard/starlabs/labtop/Kconfig
@@ -13,6 +13,15 @@ config BOARD_STARLABS_LABTOP_SERIES
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SYSTEM_TYPE_LAPTOP
 
+config BOARD_STARLABS_LABTOP_KBL
+	select BOARD_ROMSIZE_KB_8192
+	select BOARD_STARLABS_LABTOP_SERIES
+	select HAVE_INTEL_PTT
+	select HAVE_SPD_IN_CBFS
+	select MAINBOARD_HAS_LIBGFXINIT
+	select SOC_INTEL_KABYLAKE
+	select SPI_FLASH_GIGADEVICE
+
 config BOARD_STARLABS_LABTOP_CML
 	select BOARD_ROMSIZE_KB_16384
 	select BOARD_STARLABS_LABTOP_SERIES
@@ -47,6 +56,9 @@ if BOARD_STARLABS_LABTOP_SERIES
 config DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
 
+config DIMM_SPD_SIZE
+	default 512 if BOARD_STARLABS_LABTOP_KBL
+
 config DRIVER_TPM_SPI_CHIP
 	default 2
 
@@ -63,6 +75,7 @@ config EC_STARLABS_ITE_BIN_PATH
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
 
 config EC_VARIANT_DIR
+	default "kbl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_KBL
 	default "cml" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_CML
 	default "tgl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_STARBOOK_TGL
 
@@ -78,10 +91,12 @@ config MAINBOARD_DIR
 
 config MAINBOARD_FAMILY
 	string
+	default "L3" if BOARD_STARLABS_LABTOP_KBL
 	default "L4" if BOARD_STARLABS_LABTOP_CML
 	default "B5" if BOARD_STARLABS_STARBOOK_TGL
 
 config MAINBOARD_PART_NUMBER
+	default "LabTop Mk III" if BOARD_STARLABS_LABTOP_KBL
 	default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML
 	default "StarBook Mk V" if BOARD_STARLABS_STARBOOK_TGL
 
@@ -104,6 +119,7 @@ config USE_PM_ACPI_TIMER
 	default n if BOARD_STARLABS_STARBOOK_TGL
 
 config VARIANT_DIR
+	default "kbl" if BOARD_STARLABS_LABTOP_KBL
 	default "cml" if BOARD_STARLABS_LABTOP_CML
 	default "tgl" if BOARD_STARLABS_STARBOOK_TGL
 

diff --git a/src/mainboard/starlabs/labtop/Kconfig.name b/src/mainboard/starlabs/labtop/Kconfig.name
@@ -1,5 +1,8 @@
 comment "Star Labs LabTop Series"
 
+config BOARD_STARLABS_LABTOP_KBL
+	bool "Star Labs LabTop Mk III (i7-8550u)"
+
 config BOARD_STARLABS_LABTOP_CML
 	bool "Star Labs LabTop Mk IV (i3-10110U and i7-10710U)"
 

diff --git a/src/mainboard/starlabs/labtop/acpi/ec.asl b/src/mainboard/starlabs/labtop/acpi/ec.asl
@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
diff --git a/src/mainboard/starlabs/labtop/acpi/superio.asl b/src/mainboard/starlabs/labtop/acpi/superio.asl
@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
diff --git a/src/mainboard/starlabs/labtop/dsdt.asl b/src/mainboard/starlabs/labtop/dsdt.asl
@@ -17,7 +17,11 @@ DefinitionBlock(
 
 	Device (\_SB.PCI0)
 	{
-#if CONFIG(SOC_INTEL_CANNONLAKE_BASE)
+#if CONFIG(SOC_INTEL_COMMON_SKYLAKE_BASE)
+		/* Kaby Lake */
+		#include <soc/intel/skylake/acpi/systemagent.asl>
+		#include <soc/intel/skylake/acpi/pch.asl>
+#elif CONFIG(SOC_INTEL_CANNONLAKE_BASE)
 		/* Comet Lake */
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>

diff --git a/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += romstage.c
+
+ramstage-y += devtree.c
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/board.fmd b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd
@@ -0,0 +1,9 @@
+FLASH 8M {
+	BIOS@0x200000 0x600000 {
+		RW_MRC_CACHE@0x0 0x10000
+		SMMSTORE@0x10000 0x40000
+		CONSOLE@0x50000 0x20000
+		FMAP@0x70000 0x200
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/data.vbt b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb
@@ -0,0 +1,184 @@
+chip soc/intel/skylake
+# CPU
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable"			= "1"
+
+	# Graphics
+	# IGD Displays
+	register "panel_cfg" = "{
+		.up_delay_ms			=  0,				// T3
+		.backlight_on_delay_ms		=  0,				// T7
+		.backlight_off_delay_ms		=  0,				// T9
+		.down_delay_ms			=  0,				// T10
+		.cycle_delay_ms			=  500,				// T12
+		.backlight_pwm_hz		=  200,				// PWM
+	}"
+
+	# FSP Memory
+	register "SaGv"				= "SaGv_Enabled"
+
+# FSP Silicon
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]		= PchSerialIoPci,
+		[PchSerialIoIndexUart2]		= PchSerialIoSkipInit,
+	}"
+
+	# Power
+	register "PmConfigSlpS3MinAssert"	= "2"				# 50ms
+	register "PmConfigSlpS4MinAssert"	= "3"				# 1s
+	register "PmConfigSlpSusMinAssert"	= "3"				# 500ms
+	register "PmConfigSlpAMinAssert"	= "3"				# 2s
+
+	# Thermal
+	register "tcc_offset"			= "10"
+
+	# PM Util
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0"			= "GPP_B"
+	register "gpe0_dw1"			= "GPP_C"
+	register "gpe0_dw2"			= "GPP_E"
+
+	# Enable the correct decode ranges on the LPC bus.
+	register "lpc_ioe"			= "LPC_IOE_EC_4E_4F |
+						   LPC_IOE_KBC_60_64 |
+						   LPC_IOE_EC_62_66"
+
+# Actual device tree.
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end						# Host Bridge
+		device pci 02.0 on  end						# Integrated Graphics Device
+		device pci 04.0 on  end						# SA Thermal Device
+		device pci 14.0 on						# USB xHCI
+			### USB 2.0 Devices
+			# Motherboard USB Type C
+			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			# Motherboard USB 3.0
+			register "usb2_ports[1]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Daughterboard USB 3.0
+			register "usb2_ports[2]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Internal Webcam
+			register "usb2_ports[3]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Internal Bluetooth
+			register "usb2_ports[5]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Daughterboard SD Card
+			register "usb2_ports[6]"		= "USB2_PORT_MID(OC_SKIP)"
+
+			### USB 3.0 Devices
+			# Motherboard USB Type C
+			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			# Motherboard USB 3.0
+			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			# Daughterboard USB 3.0
+			register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+		end
+		device pci 14.1 off end						# USB xDCI (OTG)
+		device pci 14.2 on  end						# Thermal Subsystem
+		device pci 15.0 on						# I2C #0
+			chip drivers/i2c/hid
+				register "generic.hid"		= ""STAR0001""
+				register "generic.desc"		= ""Touchpad""
+				register "generic.irq"		= "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)"
+				register "generic.probed"	= "1"
+				register "hid_desc_reg_offset"	= "0x20"
+				device i2c 2c on end
+			end
+		end
+		device pci 15.1 off end						# I2C1
+		device pci 15.2 off end						# I2C2
+		device pci 15.3 off end						# I2C3
+		device pci 16.0 on  end						# Management Engine Interface 1
+		device pci 16.1 off end						# Management Engine Interface 2
+		device pci 16.2 off end						# Management Engine IDE-R
+		device pci 16.3 off end						# Management Engine KT Redirection
+		device pci 16.4 off end						# Management Engine Interface 3
+		device pci 17.0 on						# SATA
+			register "SataSalpSupport"		= "1"
+			# Port 1
+			register "SataPortsEnable[1]"		= "1"
+			register "SataPortsDevSlp[1]"		= "1"
+		end
+		device pci 19.0 on  end						# UART #2
+		device pci 19.1 off end						# I2C4
+		device pci 19.2 off end						# I2C5
+		device pci 1c.0 off end						# PCI Express Port 1
+		device pci 1c.1 off end						# PCI Express Port 2
+		device pci 1c.2 off end						# PCI Express Port 3
+		device pci 1c.3 off end						# PCI Express Port 4
+		device pci 1c.4 off end						# PCI Express Port 5
+		device pci 1c.5 on						# PCI Express Port 6
+			register "PcieRpEnable[5]"		= "1"
+			register "PcieRpClkReqSupport[5]"	= "1"
+			register "PcieRpClkReqNumber[5]"	= "4"
+			register "PcieRpClkSrcNumber[5]"	= "4"
+			register "PcieRpLtrEnable[5]"		= "1"
+			chip drivers/wifi/generic
+				device generic 0 on end
+			end
+		end
+		device pci 1c.6 off end						# PCI Express Port 7
+		device pci 1c.7 off end						# PCI Express Port 8
+		device pci 1d.0 on						# PCI Express Port 9(SSD x4)
+			register "PcieRpEnable[8]"		= "1"
+			register "PcieRpClkReqSupport[8]"	= "1"
+			register "PcieRpClkReqNumber[8]"	= "0"
+			register "PcieRpClkSrcNumber[8]"	= "0"
+			register "PcieRpLtrEnable[8]"		= "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
+		end
+		device pci 1d.1 off end						# PCI Express Port 10
+		device pci 1d.2 off end						# PCI Express Port 11
+		device pci 1d.3 off end						# PCI Express Port 12
+		device pci 1e.0 on  end						# UART #0
+		device pci 1e.1 off end						# UART #1
+		device pci 1e.2 off end						# GSPI #0
+		device pci 1e.3 off end						# GSPI #1
+		device pci 1e.4 off end						# eMMC
+		device pci 1e.5 off end						# SDIO
+		device pci 1e.6 off end						# SDCard
+		device pci 1f.0 on						# LPC Interface
+			register "gen1_dec"			= "0x000c0681"
+			register "gen2_dec"			= "0x000c1641"
+			register "gen3_dec"			= "0x00000069"
+			register "gen4_dec"			= "0x0000006d"
+
+			chip ec/starlabs/merlin
+				# Port pair 4Eh/4Fh
+				device pnp 4e.00 on  end			# IO Interface
+				device pnp 4e.01 off end			# Com 1
+				device pnp 4e.02 off end			# Com 2
+				device pnp 4e.04 off end			# System Wake-Up
+				device pnp 4e.05 off end			# PS/2 Mouse
+				device pnp 4e.06 on				# PS/2 Keyboard
+					io 0x60			= 0x0060
+					io 0x62			= 0x0064
+					irq 0x70		= 1
+				end
+				device pnp 4e.0a off end			# Consumer IR
+				device pnp 4e.0f off end			# Shared Memory/Flash Interface
+				device pnp 4e.10 off end			# RTC-like Timer
+				device pnp 4e.11 off end			# Power Management Channel 1
+				device pnp 4e.12 off end			# Power Management Channel 2
+				device pnp 4e.13 off end			# Serial Peripheral Interface
+				device pnp 4e.14 off end			# Platform EC Interface
+				device pnp 4e.17 off end			# Power Management Channel 3
+				device pnp 4e.18 off end			# Power Management Channel 4
+				device pnp 4e.19 off end			# Power Management Channel 5
+			end
+		end
+		device pci 1f.1 off end						# P2SB
+		device pci 1f.2 on  end						# Power Management Controller
+		device pci 1f.3 on  end						# Intel HDA
+		device pci 1f.4 on  end						# SMBus
+		device pci 1f.5 on  end						# PCH SPI
+		device pci 1f.6 off end						# GbE
+	end
+end