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cpu/amd/fam10h-15h: Add tsc_freq_mhz() function
The AMD Family 10h/15h processors use a TSC that increments at the P0 core frequency. Allow coreboot to query the TSC frequency. Change-Id: I73ead4fd4af18991452d59985b667a54689778cd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12834 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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/* | ||
* This file is part of the coreboot project. | ||
* | ||
* Copyright (C) 2016 Raptor Engineering | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License as published by | ||
* the Free Software Foundation; version 2 of the License. | ||
* | ||
* This program is distributed in the hope that it will be useful, | ||
* but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
* GNU General Public License for more details. | ||
*/ | ||
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#include <stdint.h> | ||
#include <cpu/x86/msr.h> | ||
#include <cpu/x86/tsc.h> | ||
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unsigned long tsc_freq_mhz(void) | ||
{ | ||
msr_t msr; | ||
uint8_t cpufid; | ||
uint8_t cpudid; | ||
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/* On Family 10h/15h CPUs the TSC increments | ||
* at the P0 clock rate. Read the P0 clock | ||
* frequency from the P0 MSR and convert | ||
* to MHz. See also the Family 15h BKDG | ||
* Rev. 3.14 page 569. | ||
*/ | ||
msr = rdmsr(0xc0010064); | ||
cpufid = (msr.lo & 0x3f); | ||
cpudid = (msr.lo & 0x1c0) >> 6; | ||
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return (100 * (cpufid + 0x10)) / (0x01 << cpudid); | ||
} |