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Even though this SoC is called 'Genoa', the openSIL implementation and the corresponding coreboot integration is only a proof of concept that isn't fully featured, has known limitations and bugs, and is not meant for or ready to being productized. Adding the proof of concept suffix to the name should point this out clearly enough so that no potential customer could infer that this might be a fully functional and supported implementation which it is not. Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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chip soc/amd/genoa | ||
chip soc/amd/genoa_poc | ||
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# USB configuration | ||
register "usb.xhci0_enable" = "1" | ||
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2 changes: 1 addition & 1 deletion
2
src/soc/amd/genoa/chipset.cb → src/soc/amd/genoa_poc/chipset.cb
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6 changes: 3 additions & 3 deletions
6
src/soc/amd/genoa/include/soc/cpu.h → src/soc/amd/genoa_poc/include/soc/cpu.h
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/* SPDX-License-Identifier: GPL-2.0-only */ | ||
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#ifndef AMD_GENOA_CPU_H | ||
#define AMD_GENOA_CPU_H | ||
#ifndef AMD_GENOA_POC_CPU_H | ||
#define AMD_GENOA_POC_CPU_H | ||
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#define GENOA_A0_CPUID CPUID_FROM_FMS(0x19, 0x10, 0) | ||
#define GENOA_B0_CPUID CPUID_FROM_FMS(0x19, 0x11, 0) | ||
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#endif /* AMD_GENOA_CPU_H */ | ||
#endif /* AMD_GENOA_POC_CPU_H */ |
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/* SPDX-License-Identifier: GPL-2.0-only */ | ||
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#ifndef _SOC_GENOA_POC_SOC_CHIP_H_ | ||
#define _SOC_GENOA_POC_SOC_CHIP_H_ | ||
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#include "../../chip.h" | ||
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#endif /* _SOC_GENOA_POC_SOC_CHIP_H_ */ |
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