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soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO
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Adding GPIO definition for community 3 which is CPU reserved GPIO used
by CPU side PCIe root ports. We did not have this definition since
FSP used to program this GPIOs. Now, instead of FSP, coreboot programs
CPU PCIe GPIOs for CLKSRC and lanes to put GPIOs in native mode.
Thus adding definition of this virtual GPIOs in this CL.

BUG=None
BRANCH=None
TEST=Check if correct registers are being programmed

Change-Id: I481ea7e3ba948bf6d37b97d08c675a18ee68125d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@Mvvaghel @felixheld
Mvvaghel authored and felixheld committed May 5, 2021
1 parent cc3637f commit e6e8b3d
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Showing 3 changed files with 237 additions and 100 deletions.
25 changes: 24 additions & 1 deletion src/soc/intel/alderlake/gpio.c
View file
Expand Up @@ -50,6 +50,10 @@ static const struct pad_group adl_community2_groups[] = {
INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */
};

/* This community is not visible to the OS */
static const struct pad_group adl_community3_groups[] = {
INTEL_GPP(GPP_CPU_RSVD_1, GPP_CPU_RSVD_1, GPP_vGPIO_PCIE_83), /* vGPIO */
};
static const struct pad_group adl_community4_groups[] = {
INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */
INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288), /* GPP_F */
Expand Down Expand Up @@ -120,6 +124,25 @@ static const struct pad_community adl_communities[] = {
.groups = adl_community2_groups,
.num_groups = ARRAY_SIZE(adl_community2_groups),
},
[COMM_3] = { /* vGPIO */
.port = PID_GPIOCOM3,
.first_pad = GPIO_COM3_START,
.last_pad = GPIO_COM3_END,
.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_VGPIO",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = adl_community3_groups,
.num_groups = ARRAY_SIZE(adl_community3_groups),
},
[COMM_4] = { /* GPP F, C, HVMOS, E */
.port = PID_GPIOCOM4,
.first_pad = GPIO_COM4_START,
Expand Down Expand Up @@ -183,4 +206,4 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
};
*num = ARRAY_SIZE(routes);
return routes;
}
};
1 change: 1 addition & 0 deletions src/soc/intel/alderlake/include/soc/gpio_defs.h
View file
Expand Up @@ -16,6 +16,7 @@
#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)

Expand Down
311 changes: 212 additions & 99 deletions src/soc/intel/alderlake/include/soc/gpio_soc_defs.h
View file
Expand Up @@ -27,9 +27,9 @@
#define COMM_0 0
#define COMM_1 1
#define COMM_2 2
/* GPIO community 3 is not exposed to be used and hence is skipped. */
#define COMM_4 3
#define COMM_5 4
#define COMM_3 3
#define COMM_4 4
#define COMM_5 5
/*
* GPIOs are ordered monotonically increasing to match ACPI/OS driver.
*/
Expand Down Expand Up @@ -196,117 +196,230 @@
#define GPIO_COM2_END GPD_DRAM_RESETB
#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1)

/* PCIE VGPIO group */
#define GPP_CPU_RSVD_1 137
#define GPP_CPU_RSVD_2 138
#define GPP_CPU_RSVD_3 139
#define GPP_CPU_RSVD_4 140
#define GPP_CPU_RSVD_5 141
#define GPP_CPU_RSVD_6 142
#define GPP_CPU_RSVD_7 143
#define GPP_CPU_RSVD_8 144
#define GPP_CPU_RSVD_9 145
#define GPP_CPU_RSVD_10 146
#define GPP_CPU_RSVD_11 147
#define GPP_CPU_RSVD_12 148
#define GPP_CPU_RSVD_13 149
#define GPP_CPU_RSVD_14 150
#define GPP_CPU_RSVD_15 151
#define GPP_vGPIO_PCIE_0 152
#define GPP_vGPIO_PCIE_1 153
#define GPP_vGPIO_PCIE_2 154
#define GPP_vGPIO_PCIE_3 155
#define GPP_vGPIO_PCIE_4 156
#define GPP_vGPIO_PCIE_5 157
#define GPP_vGPIO_PCIE_6 158
#define GPP_vGPIO_PCIE_7 159
#define GPP_vGPIO_PCIE_8 160
#define GPP_vGPIO_PCIE_9 161
#define GPP_vGPIO_PCIE_10 162
#define GPP_vGPIO_PCIE_11 163
#define GPP_vGPIO_PCIE_12 164
#define GPP_vGPIO_PCIE_13 165
#define GPP_vGPIO_PCIE_14 166
#define GPP_vGPIO_PCIE_15 167
#define GPP_vGPIO_PCIE_16 168
#define GPP_vGPIO_PCIE_17 169
#define GPP_vGPIO_PCIE_18 170
#define GPP_vGPIO_PCIE_19 171
#define GPP_vGPIO_PCIE_20 172
#define GPP_vGPIO_PCIE_21 173
#define GPP_vGPIO_PCIE_22 174
#define GPP_vGPIO_PCIE_23 175
#define GPP_vGPIO_PCIE_24 176
#define GPP_vGPIO_PCIE_25 177
#define GPP_vGPIO_PCIE_26 178
#define GPP_vGPIO_PCIE_27 179
#define GPP_vGPIO_PCIE_28 180
#define GPP_vGPIO_PCIE_29 181
#define GPP_vGPIO_PCIE_30 182
#define GPP_vGPIO_PCIE_31 183
#define GPP_vGPIO_PCIE_32 184
#define GPP_vGPIO_PCIE_33 185
#define GPP_vGPIO_PCIE_34 186
#define GPP_vGPIO_PCIE_35 187
#define GPP_vGPIO_PCIE_36 188
#define GPP_vGPIO_PCIE_37 189
#define GPP_vGPIO_PCIE_38 190
#define GPP_vGPIO_PCIE_39 191
#define GPP_vGPIO_PCIE_40 192
#define GPP_vGPIO_PCIE_41 193
#define GPP_vGPIO_PCIE_42 194
#define GPP_vGPIO_PCIE_43 195
#define GPP_vGPIO_PCIE_44 196
#define GPP_vGPIO_PCIE_45 197
#define GPP_vGPIO_PCIE_46 198
#define GPP_vGPIO_PCIE_47 199
#define GPP_vGPIO_PCIE_48 200
#define GPP_vGPIO_PCIE_49 201
#define GPP_vGPIO_PCIE_50 202
#define GPP_vGPIO_PCIE_51 203
#define GPP_vGPIO_PCIE_52 204
#define GPP_vGPIO_PCIE_53 205
#define GPP_vGPIO_PCIE_54 206
#define GPP_vGPIO_PCIE_55 207
#define GPP_vGPIO_PCIE_56 208
#define GPP_vGPIO_PCIE_57 209
#define GPP_vGPIO_PCIE_58 210
#define GPP_vGPIO_PCIE_59 211
#define GPP_vGPIO_PCIE_60 212
#define GPP_vGPIO_PCIE_61 213
#define GPP_vGPIO_PCIE_62 214
#define GPP_vGPIO_PCIE_63 215
#define GPP_vGPIO_PCIE_64 216
#define GPP_vGPIO_PCIE_65 217
#define GPP_vGPIO_PCIE_66 218
#define GPP_vGPIO_PCIE_67 219
#define GPP_vGPIO_PCIE_68 220
#define GPP_vGPIO_PCIE_69 221
#define GPP_vGPIO_PCIE_70 222
#define GPP_vGPIO_PCIE_71 223
#define GPP_vGPIO_PCIE_72 224
#define GPP_vGPIO_PCIE_73 225
#define GPP_vGPIO_PCIE_74 226
#define GPP_vGPIO_PCIE_75 227
#define GPP_vGPIO_PCIE_76 228
#define GPP_vGPIO_PCIE_77 229
#define GPP_vGPIO_PCIE_78 230
#define GPP_vGPIO_PCIE_79 231
#define GPP_CPU_RSVD_16 232
#define GPP_CPU_RSVD_17 233
#define GPP_CPU_RSVD_18 234
#define GPP_CPU_RSVD_19 235
#define GPP_CPU_RSVD_20 236
#define GPP_CPU_RSVD_21 237
#define GPP_CPU_RSVD_22 238
#define GPP_CPU_RSVD_23 239
#define GPP_vGPIO_PCIE_80 240
#define GPP_vGPIO_PCIE_81 241
#define GPP_vGPIO_PCIE_82 242
#define GPP_vGPIO_PCIE_83 243

#define GPIO_COM3_START GPP_CPU_RSVD_1
#define GPIO_COM3_END GPP_vGPIO_PCIE_83
#define NUM_GPIO_COM3_PADS (GPIO_COM3_END - GPIO_COM3_START + 1)

/* Group C */
#define GPP_C0 137
#define GPP_C1 138
#define GPP_C2 139
#define GPP_C3 140
#define GPP_C4 141
#define GPP_C5 142
#define GPP_C6 143
#define GPP_C7 144
#define GPP_C8 145
#define GPP_C9 146
#define GPP_C10 147
#define GPP_C11 148
#define GPP_C12 149
#define GPP_C13 150
#define GPP_C14 151
#define GPP_C15 152
#define GPP_C16 153
#define GPP_C17 154
#define GPP_C18 155
#define GPP_C19 156
#define GPP_C20 157
#define GPP_C21 158
#define GPP_C22 159
#define GPP_C23 160
#define GPP_C0 244
#define GPP_C1 245
#define GPP_C2 246
#define GPP_C3 247
#define GPP_C4 248
#define GPP_C5 249
#define GPP_C6 250
#define GPP_C7 251
#define GPP_C8 252
#define GPP_C9 253
#define GPP_C10 254
#define GPP_C11 255
#define GPP_C12 256
#define GPP_C13 257
#define GPP_C14 258
#define GPP_C15 259
#define GPP_C16 260
#define GPP_C17 261
#define GPP_C18 262
#define GPP_C19 263
#define GPP_C20 264
#define GPP_C21 265
#define GPP_C22 266
#define GPP_C23 267

/* Group F */
#define GPP_F0 161
#define GPP_F1 162
#define GPP_F2 163
#define GPP_F3 164
#define GPP_F4 165
#define GPP_F5 166
#define GPP_F6 167
#define GPP_F7 168
#define GPP_F8 169
#define GPP_F9 170
#define GPP_F10 171
#define GPP_F11 172
#define GPP_F12 173
#define GPP_F13 174
#define GPP_F14 175
#define GPP_F15 176
#define GPP_F16 177
#define GPP_F17 178
#define GPP_F18 179
#define GPP_F19 180
#define GPP_F20 181
#define GPP_F21 182
#define GPP_F22 183
#define GPP_F23 184
#define GPP_F_CLK_LOOPBK 185
#define GPP_F0 268
#define GPP_F1 269
#define GPP_F2 270
#define GPP_F3 271
#define GPP_F4 272
#define GPP_F5 273
#define GPP_F6 274
#define GPP_F7 275
#define GPP_F8 276
#define GPP_F9 277
#define GPP_F10 278
#define GPP_F11 279
#define GPP_F12 280
#define GPP_F13 281
#define GPP_F14 282
#define GPP_F15 283
#define GPP_F16 284
#define GPP_F17 285
#define GPP_F18 286
#define GPP_F19 287
#define GPP_F20 288
#define GPP_F21 289
#define GPP_F22 290
#define GPP_F23 291
#define GPP_F_CLK_LOOPBK 292

/* Group HVMOS */
#define GPP_L_BKLTEN 186
#define GPP_L_BKLTCTL 187
#define GPP_L_VDDEN 188
#define GPP_SYS_PWROK 189
#define GPP_SYS_RESETB 190
#define GPP_MLK_RSTB 191
#define GPP_L_BKLTEN 293
#define GPP_L_BKLTCTL 294
#define GPP_L_VDDEN 295
#define GPP_SYS_PWROK 296
#define GPP_SYS_RESETB 297
#define GPP_MLK_RSTB 298

/* Group E */
#define GPP_E0 192
#define GPP_E1 193
#define GPP_E2 194
#define GPP_E3 195
#define GPP_E4 196
#define GPP_E5 197
#define GPP_E6 198
#define GPP_E7 199
#define GPP_E8 200
#define GPP_E9 201
#define GPP_E10 202
#define GPP_E11 203
#define GPP_E12 204
#define GPP_E13 205
#define GPP_E14 206
#define GPP_E15 207
#define GPP_E16 208
#define GPP_E17 209
#define GPP_E18 210
#define GPP_E19 211
#define GPP_E20 212
#define GPP_E21 213
#define GPP_E22 214
#define GPP_E23 215
#define GPP_E_CLK_LOOPBK 216
#define GPP_E0 299
#define GPP_E1 300
#define GPP_E2 301
#define GPP_E3 302
#define GPP_E4 303
#define GPP_E5 304
#define GPP_E6 305
#define GPP_E7 306
#define GPP_E8 307
#define GPP_E9 308
#define GPP_E10 309
#define GPP_E11 310
#define GPP_E12 311
#define GPP_E13 312
#define GPP_E14 313
#define GPP_E15 314
#define GPP_E16 315
#define GPP_E17 316
#define GPP_E18 317
#define GPP_E19 318
#define GPP_E20 319
#define GPP_E21 320
#define GPP_E22 321
#define GPP_E23 322
#define GPP_E_CLK_LOOPBK 323

#define GPIO_COM4_START GPP_C0
#define GPIO_COM4_END GPP_E_CLK_LOOPBK
#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1)

/* Group R */
#define GPP_R0 217
#define GPP_R1 218
#define GPP_R2 219
#define GPP_R3 220
#define GPP_R4 221
#define GPP_R5 222
#define GPP_R6 223
#define GPP_R7 224
#define GPP_R0 324
#define GPP_R1 325
#define GPP_R2 326
#define GPP_R3 327
#define GPP_R4 328
#define GPP_R5 329
#define GPP_R6 330
#define GPP_R7 331

/* Group SPI0 */
#define GPP_SPI0_IO_2 225
#define GPP_SPI0_IO_3 226
#define GPP_SPI0_MOSI_IO_0 227
#define GPP_SPI0_MOSI_IO_1 228
#define GPP_SPI0_TPM_CSB 229
#define GPP_SPI0_FLASH_0_CSB 230
#define GPP_SPI0_FLASH_1_CSB 231
#define GPP_SPI0_CLK 232
#define GPP_SPI0_IO_2 332
#define GPP_SPI0_IO_3 333
#define GPP_SPI0_MOSI_IO_0 334
#define GPP_SPI0_MOSI_IO_1 335
#define GPP_SPI0_TPM_CSB 336
#define GPP_SPI0_FLASH_0_CSB 337
#define GPP_SPI0_FLASH_1_CSB 338
#define GPP_SPI0_CLK 339

#define GPIO_COM5_START GPP_R0
#define GPIO_COM5_END GPP_SPI0_CLK
Expand Down

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