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mb/google/brya/variants/osiris: Configure GPIOs according to schematics
Update initial gpio configuration for osiris BUG=b:224423318 TEST=FW_NAME=osiris emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I014bd7ebf94bf687362f7ee734cadfa83f3bde2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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# SPDX-License-Identifier: GPL-2.0-only | ||
bootblock-y += gpio.c | ||
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romstage-y += gpio.c | ||
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ramstage-y += gpio.c |
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/* SPDX-License-Identifier: GPL-2.0-or-later */ | ||
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#include <baseboard/gpio.h> | ||
#include <baseboard/variants.h> | ||
#include <commonlib/helpers.h> | ||
#include <soc/gpio.h> | ||
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/* Pad configuration in ramstage */ | ||
static const struct pad_config override_gpio_table[] = { | ||
/* A6 : ESPI_ALERT1# ==> NC */ | ||
PAD_NC(GPP_A6, NONE), | ||
/* A7 : SRCCLK_OE7# ==> LAN_WAKE_ODL */ | ||
PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE), | ||
/* A8 : SRCCLKREQ7# ==> NC */ | ||
PAD_NC(GPP_A8, NONE), | ||
/* A12 : SATAXPCIE1 ==> NC */ | ||
PAD_NC(GPP_A12, NONE), | ||
/* A15 : USB_OC2# ==> NC */ | ||
PAD_NC(GPP_A15, NONE), | ||
/* A19 : DDSP_HPD1 ==> NC */ | ||
PAD_NC(GPP_A19, NONE), | ||
/* A20 : DDSP_HPD2 ==> NC */ | ||
PAD_NC(GPP_A20, NONE), | ||
/* A21 : DDPC_CTRCLK ==> NC */ | ||
PAD_NC(GPP_A21, NONE), | ||
/* A22 : DDPC_CTRLDATA ==> NC */ | ||
PAD_NC(GPP_A22, NONE), | ||
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/* B2 : VRALERT# ==> NC */ | ||
PAD_NC(GPP_B2, NONE), | ||
/* B3 : PROC_GP2 ==> NC */ | ||
PAD_NC(GPP_B3, NONE), | ||
/* B7 : ISH_12C1_SDA ==> NC */ | ||
PAD_NC(GPP_B7, NONE), | ||
/* B8 : ISH_I2C1_SCL ==> NC */ | ||
PAD_NC(GPP_B8, NONE), | ||
/* B15 : TIME_SYNC0 ==> NC */ | ||
PAD_NC(GPP_B15, NONE), | ||
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/* C0 : SMBCLK ==> NC */ | ||
PAD_NC(GPP_C0, NONE), | ||
/* C1 : SMBDATA ==> NC */ | ||
PAD_NC(GPP_C1, NONE), | ||
/* C3 : SML0CLK ==> NC */ | ||
PAD_NC(GPP_C3, NONE), | ||
/* C4 : SML0DATA ==> NC */ | ||
PAD_NC(GPP_C4, NONE), | ||
/* C6 : SML1CLK ==> NC */ | ||
PAD_NC(GPP_C6, NONE), | ||
/* C7 : SML1DATA ==> NC */ | ||
PAD_NC(GPP_C7, NONE), | ||
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/* D0 : ISH_GP0 ==> NC */ | ||
PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), | ||
/* D1 : ISH_GP1 ==> NC */ | ||
PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), | ||
/* D2 : ISH_GP2 ==> NC */ | ||
PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), | ||
/* D3 : ISH_GP3 ==> NC */ | ||
PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), | ||
/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ | ||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), | ||
/* D6 : SRCCLKREQ1# ==> NC */ | ||
PAD_NC(GPP_D6, NONE), | ||
/* D7 : SRCCLKREQ2# ==> NC */ | ||
PAD_NC(GPP_D7, NONE), | ||
/* D8 : SRCCLKREQ3# ==> NC */ | ||
PAD_NC(GPP_D8, NONE), | ||
/* D9 : ISH_SPI_CS# ==> NC */ | ||
PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), | ||
/* D13 : ISH_UART0_RXD ==> NC */ | ||
PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), | ||
/* D14 : ISH_UART0_TXD ==> NC */ | ||
PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), | ||
/* D15 : ISH_UART0_RTS# ==> NC */ | ||
PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), | ||
/* D16 : ISH_UART0_CTS# ==> NC */ | ||
PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), | ||
/* D17 : UART1_RXD ==> NC */ | ||
PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), | ||
/* D18 : UART1_TXD ==> NC */ | ||
PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG), | ||
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/* E0 : SATAXPCIE0 ==> NC */ | ||
PAD_NC(GPP_E0, NONE), | ||
/* E3 : PROC_GP0 ==> NC */ | ||
PAD_NC(GPP_E3, NONE), | ||
/* E4 : SATA_DEVSLP0 ==> NC */ | ||
PAD_NC(GPP_E4, NONE), | ||
/* E7 : PROC_GP1 ==> NC */ | ||
PAD_NC(GPP_E7, NONE), | ||
/* E10 : THC0_SPI1_CS# ==> NC */ | ||
PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), | ||
/* E16 : RSVD_TP ==> NC */ | ||
PAD_NC(GPP_E16, NONE), | ||
/* E17 : THC0_SPI1_INT# ==> NC */ | ||
PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), | ||
/* E18 : DDP1_CTRLCLK ==> NC */ | ||
PAD_NC(GPP_E18, NONE), | ||
/* E20 : DDP2_CTRLCLK ==> NC */ | ||
PAD_NC(GPP_E20, NONE), | ||
/* E22 : DDPA_CTRLCLK ==> NC */ | ||
PAD_NC(GPP_E22, NONE), | ||
/* E23 : DDPA_CTRLDATA ==> NC */ | ||
PAD_NC(GPP_E23, NONE), | ||
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/* F6 : CNV_PA_BLANKING ==> NC */ | ||
PAD_NC(GPP_F6, NONE), | ||
/* F11 : THC1_SPI2_CLK ==> NC */ | ||
PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), | ||
/* F12 : GSXDOUT ==> NC */ | ||
PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), | ||
/* F13 : GSXDOUT ==> NC */ | ||
PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), | ||
/* F15 : GSXSRESET# ==> NC */ | ||
PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), | ||
/* F16 : GSXCLK ==> NC */ | ||
PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), | ||
/* F19 : SRCCLKREQ6# ==> LAN_CLKREQ_ODL */ | ||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), | ||
/* F20 : EXT_PWR_GATE# ==> NC */ | ||
PAD_NC(GPP_F20, NONE), | ||
/* F21 : EXT_PWR_GATE2# ==> NC */ | ||
PAD_NC(GPP_F21, NONE), | ||
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/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ | ||
PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), | ||
/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ | ||
PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), | ||
/* H8 : I2C4_SDA ==> NC */ | ||
PAD_NC(GPP_H8, NONE), | ||
/* H9 : I2C4_SCL ==> NC */ | ||
PAD_NC(GPP_H9, NONE), | ||
/* H12 : I2C7_SDA ==> NC */ | ||
PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), | ||
/* H19 : SRCCLKREQ4# ==> NC */ | ||
PAD_NC(GPP_H19, NONE), | ||
/* H20 : IMGCLKOUT1 ==> NC */ | ||
PAD_NC(GPP_H20, NONE), | ||
/* H21 : IMGCLKOUT2 ==> NC */ | ||
PAD_NC(GPP_H21, NONE), | ||
/* H22 : IMGCLKOUT3 ==> LAN_PE_ISOLATE_ODL */ | ||
PAD_CFG_GPO(GPP_H22, 1, DEEP), | ||
/* H23 : SRCCLKREQ5# ==> NC */ | ||
PAD_NC(GPP_H23, NONE), | ||
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/* R4 : HDA_RST# ==> DMIC_CLK0_R */ | ||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), | ||
/* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ | ||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), | ||
/* R6 : I2S2_TXD ==> DMIC_CLK1_R */ | ||
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), | ||
/* R7 : I2S2_RXD ==> DMIC_DATA1_R */ | ||
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), | ||
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/* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ | ||
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), | ||
/* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */ | ||
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), | ||
/* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */ | ||
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), | ||
/* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */ | ||
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), | ||
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/* GPD11: LANPHYC ==> NC */ | ||
PAD_NC(GPD11, NONE), | ||
}; | ||
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/* Early pad configuration in bootblock */ | ||
static const struct pad_config early_gpio_table[] = { | ||
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ | ||
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), | ||
/* B4 : PROC_GP3 ==> SSD_PERST_L */ | ||
PAD_CFG_GPO(GPP_B4, 0, DEEP), | ||
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/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ | ||
PAD_CFG_GPO(GPP_D11, 1, DEEP), | ||
/* E0 : SATAXPCIE0 ==> NC */ | ||
PAD_NC(GPP_E0, NONE), | ||
/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ | ||
PAD_CFG_GPI(GPP_E13, NONE, DEEP), | ||
/* E15 : RSVD_TP ==> PCH_WP_OD */ | ||
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), | ||
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ | ||
PAD_CFG_GPI(GPP_F18, NONE, DEEP), | ||
/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ | ||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), | ||
/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ | ||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), | ||
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ | ||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), | ||
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ | ||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), | ||
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/* CPU PCIe VGPIO for PEG60 */ | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), | ||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), | ||
}; | ||
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static const struct pad_config romstage_gpio_table[] = { | ||
/* B4 : PROC_GP3 ==> SSD_PERST_L */ | ||
PAD_CFG_GPO(GPP_B4, 1, DEEP), | ||
}; | ||
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const struct pad_config *variant_gpio_override_table(size_t *num) | ||
{ | ||
*num = ARRAY_SIZE(override_gpio_table); | ||
return override_gpio_table; | ||
} | ||
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const struct pad_config *variant_early_gpio_table(size_t *num) | ||
{ | ||
*num = ARRAY_SIZE(early_gpio_table); | ||
return early_gpio_table; | ||
} | ||
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const struct pad_config *variant_romstage_gpio_table(size_t *num) | ||
{ | ||
*num = ARRAY_SIZE(romstage_gpio_table); | ||
return romstage_gpio_table; | ||
} |