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mb/google/nissa/var/quandiso: Update initial files based on yavilla
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Update files copied from yavilla
- fw_config setting
- GPIO setting
- Kconfig setting
- overridetree setting
- SPD memory parts
- variant setting

BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
flash bin file in DUT

Change-Id: Ibbef42a1f891d0cf0309aa76edd7ec5dd664588e
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77361
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@felixheld
Robert Chen authored and felixheld committed Sep 22, 2023
1 parent cce6d13 commit ff15396
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Showing 11 changed files with 869 additions and 8 deletions.
1 change: 1 addition & 0 deletions src/mainboard/google/brya/Kconfig
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Expand Up @@ -171,6 +171,7 @@ config DRIVER_TPM_I2C_BUS
default 0x0 if BOARD_GOOGLE_GOTHRAX
default 0x0 if BOARD_GOOGLE_PIRRHA
default 0x1 if BOARD_GOOGLE_DOCHI
default 0x0 if BOARD_GOOGLE_QUANDISO

config DRIVER_TPM_I2C_ADDR
hex
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12 changes: 8 additions & 4 deletions src/mainboard/google/brya/Kconfig.name
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Expand Up @@ -288,6 +288,14 @@ config BOARD_GOOGLE_PUJJO
select HAVE_WWAN_POWER_SEQUENCE
select INTEL_GMA_HAVE_VBT

config BOARD_GOOGLE_QUANDISO
bool "-> Quandiso"
select BOARD_GOOGLE_BASEBOARD_NISSA
select CHROMEOS_WIFI_SAR if CHROMEOS
select DRIVERS_GENERIC_GPIO_KEYS
select DRIVERS_INTEL_MIPI_CAMERA
select HAVE_WWAN_POWER_SEQUENCE

config BOARD_GOOGLE_REDRIX
bool "-> Redrix"
select BOARD_GOOGLE_BASEBOARD_BRYA
Expand Down Expand Up @@ -430,10 +438,6 @@ config BOARD_GOOGLE_ZYDRON
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_RAPTORLAKE

config BOARD_GOOGLE_QUANDISO
bool "-> Quandiso"
select BOARD_GOOGLE_BASEBOARD_NISSA

config BOARD_GOOGLE_NOKRIS
bool "-> Nokris"
select BOARD_GOOGLE_BASEBOARD_NISSA
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8 changes: 8 additions & 0 deletions src/mainboard/google/brya/variants/quandiso/Makefile.inc
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@@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c

romstage-y += gpio.c

ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
ramstage-$(CONFIG_FW_CONFIG) += variant.c
ramstage-y += gpio.c
101 changes: 101 additions & 0 deletions src/mainboard/google/brya/variants/quandiso/fw_config.c
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@@ -0,0 +1,101 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <console/console.h>
#include <fw_config.h>


static const struct pad_config lte_disable_pads[] = {
/* A8 : WWAN_RF_DISABLE_ODL */
PAD_NC(GPP_A8, NONE),
/* D6 : WWAN_EN */
PAD_NC(GPP_D6, NONE),
/* F12 : WWAN_RST_L */
PAD_NC(GPP_F12, NONE),
/* H23 : WWAN_SAR_DETECT_ODL */
PAD_NC(GPP_H23, NONE),
};

static const struct pad_config wfc_disable_pads[] = {
/* D3 : WCAM_RST_L */
PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D15 : EN_PP2800_WCAM_X */
PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
/* D16 : EN_PP1800_PP1200_WCAM_X */
PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
/* H22 : WCAM_MCLK_R */
PAD_NC(GPP_H22, NONE),
/* R6 : DMIC_WCAM_CLK_R */
PAD_NC(GPP_R6, NONE),
/* R7 : DMIC_WCAM_DATA */
PAD_NC(GPP_R7, NONE),
};

static const struct pad_config emmc_disable_pads[] = {
/* I7 : EMMC_CMD */
PAD_NC(GPP_I7, NONE),
/* I8 : EMMC_D0 */
PAD_NC(GPP_I8, NONE),
/* I9 : EMMC_D1 */
PAD_NC(GPP_I9, NONE),
/* I10 : EMMC_D2 */
PAD_NC(GPP_I10, NONE),
/* I11 : EMMC_D3 */
PAD_NC(GPP_I11, NONE),
/* I12 : EMMC_D4 */
PAD_NC(GPP_I12, NONE),
/* I13 : EMMC_D5 */
PAD_NC(GPP_I13, NONE),
/* I14 : EMMC_D6 */
PAD_NC(GPP_I14, NONE),
/* I15 : EMMC_D7 */
PAD_NC(GPP_I15, NONE),
/* I16 : EMMC_RCLK */
PAD_NC(GPP_I16, NONE),
/* I17 : EMMC_CLK */
PAD_NC(GPP_I17, NONE),
/* I18 : EMMC_RST_L */
PAD_NC(GPP_I18, NONE),
};

static const struct pad_config stylus_disable_pads[] = {
/* F13 : SOC_PEN_DETECT_R_ODL */
PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
/* F15 : SOC_PEN_DETECT_ODL */
PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
};

static const struct pad_config disable_wifi_pch_susclk[] = {
/* GPD8 ==> NC */
PAD_NC(GPD8, NONE),
};

void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
{
if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n");
gpio_padbased_override(padbased_table, lte_disable_pads,
ARRAY_SIZE(lte_disable_pads));
}
if (fw_config_probe(FW_CONFIG(WFC, WFC_ABSENT))) {
printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n");
gpio_padbased_override(padbased_table, wfc_disable_pads,
ARRAY_SIZE(wfc_disable_pads));
}
if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
printk(BIOS_INFO, "Disable eMMC GPIO pins.\n");
gpio_padbased_override(padbased_table, emmc_disable_pads,
ARRAY_SIZE(emmc_disable_pads));
}
if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) {
printk(BIOS_INFO, "Disable Stylus GPIO pins.\n");
gpio_padbased_override(padbased_table, stylus_disable_pads,
ARRAY_SIZE(stylus_disable_pads));
}
if (fw_config_probe(FW_CONFIG(WIFI_SAR_ID, SAR_ID_3))) {
printk(BIOS_INFO, "Disable PCH SUSCLK.\n");
gpio_padbased_override(padbased_table, disable_wifi_pch_susclk,
ARRAY_SIZE(disable_wifi_pch_susclk));
}
}
101 changes: 101 additions & 0 deletions src/mainboard/google/brya/variants/quandiso/gpio.c
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@@ -0,0 +1,101 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <soc/gpio.h>

/* Pad configuration in ramstage */
static const struct pad_config override_gpio_table[] = {
/* A8 : WWAN_RF_DISABLE_ODL */
PAD_CFG_GPO(GPP_A8, 1, DEEP),
/* A18 : NC ==> HDMI_HPD_SRC */
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
/* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
PAD_CFG_GPO(GPP_A21, 0, DEEP),
/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
PAD_CFG_GPO(GPP_A22, 1, DEEP),

/* D6 : WWAN_EN */
PAD_CFG_GPO(GPP_D6, 1, DEEP),
/* D8 : SD_CLKREQ_ODL ==> NC */
PAD_NC(GPP_D8, NONE),

/* F6 : CNV_PA_BLANKING ==> NC */
PAD_NC(GPP_F6, NONE),
/* F12 : WWAN_RST_ODL */
PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
/* F23 : V1P05EXT_CTRL ==> NC */
PAD_NC(GPP_F23, NONE),

/* H8 : CNV_MFUART2_RXD ==> NC */
PAD_NC(GPP_H8, NONE),
/* H9 : CNV_MFUART2_TXD ==> NC */
PAD_NC(GPP_H9, NONE),
/* H12 : SD_PERST_L ==> NC */
PAD_NC(GPP_H12, NONE),
/* H13 : EN_PP3300_SD_X ==> NC */
PAD_NC(GPP_H13, NONE),
/* H15 : HDMI_SRC_SCL */
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
/* H17 : HDMI_SRC_SDA */
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
/* H19 : SRCCLKREQ4# ==> NC */
PAD_NC(GPP_H19, NONE),
/* H23 : WWAN_SAR_DETECT_ODL */
PAD_CFG_GPO(GPP_H23, 1, DEEP),
};

/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* D6 : WWAN_EN */
PAD_CFG_GPO(GPP_D6, 0, DEEP),
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
PAD_CFG_GPO(GPP_H20, 0, DEEP),
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */
PAD_CFG_GPO(GPP_B11, 1, DEEP),
/* F12 : WWAN_RST_ODL */
PAD_CFG_GPO(GPP_F12, 0, DEEP),
};

static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreen, hold in reset */
/* C0 : SMBCLK ==> EN_PP3300_TCHSCR */
PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C1 : SMBDATA ==> USI_RST_L */
PAD_CFG_GPO(GPP_C1, 0, DEEP),
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
PAD_CFG_GPO(GPP_H20, 1, DEEP),
};

const struct pad_config *variant_gpio_override_table(size_t *num)
{
*num = ARRAY_SIZE(override_gpio_table);
return override_gpio_table;
}

const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}

const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}
4 changes: 4 additions & 0 deletions src/mainboard/google/brya/variants/quandiso/include/variant/gpio.h
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Expand Up @@ -5,4 +5,8 @@

#include <baseboard/gpio.h>

#define WWAN_FCPO GPP_D6
#define WWAN_RST GPP_F12
#define T2_OFF_MS 20

#endif
12 changes: 10 additions & 2 deletions src/mainboard/google/brya/variants/quandiso/memory/Makefile.inc
View file
@@ -1,5 +1,13 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
# Generated by:
# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/quandiso/memory src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt

SPD_SOURCES = placeholder
SPD_SOURCES =
SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B
SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT
SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 4(0b0100) Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
SPD_SOURCES += spd/lp5/set-0/spd-6.hex # ID = 5(0b0101) Parts = H58G66AK6BX070
SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 6(0b0110) Parts = K3KL6L60GM-MGCT
20 changes: 20 additions & 0 deletions src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
View file
@@ -1 +1,21 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# ./util/spd_tools/bin/part_id_gen ADL lp5
src/mainboard/google/brya/variants/quandiso/memory
src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt

DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)
H58G56BK7BX068 3 (0011)
MT62F1G32D2DS-026 WT:B 3 (0011)
K3KL8L80CM-MGCT 3 (0011)
H58G66BK7BX067 4 (0100)
MT62F2G32D4DS-026 WT:B 4 (0100)
K3KL9L90CM-MGCT 4 (0100)
H58G66AK6BX070 5 (0101)
K3KL6L60GM-MGCT 6 (0110)
13 changes: 13 additions & 0 deletions src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
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Expand Up @@ -9,3 +9,16 @@
# See util/spd_tools/README.md for more details and instructions.

# Part Name
MT62F512M32D2DR-031 WT:B
MT62F1G32D4DR-031 WT:B
H9JCNNNBK3MLYR-N6E
H58G56AK6BX069
K3LKBKB0BM-MGCP
H58G56BK7BX068
MT62F1G32D2DS-026 WT:B
K3KL8L80CM-MGCT
H58G66BK7BX067
MT62F2G32D4DS-026 WT:B
K3KL9L90CM-MGCT
H58G66AK6BX070
K3KL6L60GM-MGCT

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