The port control register block has a header with type 0x0000C003, version 0x00000200, and contains several port-level control registers.
| Address | Field | 31..24 | 23..16 | 15..8 | 7..0 | Reset value |
|---|---|---|---|---|---|---|
| RBB+0x00 | Type | Vendor I | D | Type | RO 0x0000C003 | |
| -------- | ------------- | -------- | ------ | -------- | ------ | ------------- |
| RBB+0x04 | Version | Major | Minor | Patch | Meta | RO 0x00000200 |
| -------- | ------------- | ------ | ------ | ------ | ------ | ------------- |
| RBB+0x08 | Next pointer | Pointer | to next | register |
|
RO - |
--------RBB+0x0C |
-------------Features |
--------Port fea |
--------ture bit |
--------s |
-------------RO - |
|
--------RBB+0x10 |
-------------TX control |
--------TX contr |
--------ol/statu |
--------s |
-------------RW 0x00000000 |
|
--------RBB+0x14 |
-------------RX control |
--------RX contr |
--------ol/statu |
--------s |
-------------RW 0x00000000 |
|
| -------- | ------------- | -------- | -------- | -------- | ------ | ------------- |
| RBB+0x18 | FC ctrl | RX quant | a step | TX quant | a step | RW - |
--------RBB+0x1C |
-------------LFC ctrl |
--------ctrl |
------LFC wate |
--------rmark |
-------------RW 0x00000000 |
|
--------RBB+0x20 |
-------------PFC ctrl 0 |
------ctrl |
--------PFC wate |
--------rmark 0 |
-------------RW 0x00000000 |
|
--------RBB+0x24 |
-------------PFC ctrl 1 |
------ctrl |
--------PFC wate |
--------rmark 1 |
-------------RW 0x00000000 |
|
--------RBB+0x28 |
-------------PFC ctrl 2 |
------ctrl |
--------PFC wate |
--------rmark 2 |
-------------RW 0x00000000 |
|
--------RBB+0x2C |
-------------PFC ctrl 3 |
------ctrl |
--------PFC wate |
--------rmark 3 |
-------------RW 0x00000000 |
|
--------RBB+0x30 |
-------------PFC ctrl 4 |
------ctrl |
--------PFC wate |
--------rmark 4 |
-------------RW 0x00000000 |
|
--------RBB+0x34 |
-------------PFC ctrl 5 |
------ctrl |
--------PFC wate |
--------rmark 5 |
-------------RW 0x00000000 |
|
--------RBB+0x38 |
-------------PFC ctrl 6 |
------ctrl |
--------PFC wate |
--------rmark 6 |
-------------RW 0x00000000 |
|
--------RBB+0x3C |
-------------PFC ctrl 7 |
------ctrl |
--------PFC wate |
--------rmark 7 |
-------------RW 0x00000000 |
See rb_overview for definitions of the standard register block header fields.
Features
The features field contains all of the port-level feature bits, indicating the state of various optional features that can be enabled via Verilog parameters during synthesis.
| Address | 31..24 | 23..16 | 15..8 | 7..0 | Reset value |
|---|---|---|---|---|---|
| RBB+0x0C | Interfac | e featur | e bits | RO - |
Currently implemented feature bits:
| Bit | Feature |
|---|---|
| 0 | LFC (IEEE 802.3 annex 31B) |
| 1 | PFC (IEEE 802.3 annex 31D) |
| 2 | Internal MAC control |
TX control/status
The TX control/status field contains some high-level control and status registers for the transmit side of the link associated with the port.
| Address | 31..24 | 23..16 | 15..8 | 7..0 | Reset value |
|---|---|---|---|---|---|
| RBB+0x10 | TX contr | ol/statu | s | RW 0x00000000 |
Control bits:
| Bit | Function |
|---|---|
| 0 | TX enable |
| 8 | TX pause control (halt TX traffic) |
| 16 | TX status (link is ready) |
| 17 | TX reset status (MAC TX is in reset) |
| 24 | TX pause req status |
| 25 | TX pause ack status |
RX control/status
The RX control/status field contains some high-level control and status registers for the receive side of the link associated with the port.
| Address | 31..24 | 23..16 | 15..8 | 7..0 | Reset value |
|---|---|---|---|---|---|
| RBB+0x14 | RX contr | ol/statu | s | RO - |
Status bits:
| Bit | Function |
|---|---|
| 0 | RX enable |
| 8 | RX pause control (halt RX traffic) |
| 16 | RX status (link is ready) |
| 17 | RX reset status (MAC RX is in reset) |
| 24 | RX pause req status |
| 25 | RX pause ack status |
FC control
The FC control field contains the quanta step size per clock cycle in units of 1/256 of one quanta for the internal MAC control layer. Default value is based on the MAC interface width.
| Address | 31..24 | 23..16 | 15..8 | 7..0 | Reset value |
|---|---|---|---|---|---|
| RBB+0x18 | RX quant | a step | TX quant | a step | RW - |
LFC control
The LFC control field contains control and status registers for link-level flow control (LFC) (IEEE 802.3 annex 31B pause frames).
| Address | 31..24 | 23..16 | 15..8 | 7..0 | Reset value |
|---|---|---|---|---|---|
| RBB+0x1C | ctrl | LFC wate | rmark | RW 0x00000000 |
control bits:
| Bit | Function |
|---|---|
| 24 | TX LFC en |
| 25 | RX LFC en |
| 28 | TX LFC req |
| 29 | RX LFC req |
PFC control N
The PFC control field contains control and status registers for priority flow control (PFC) (IEEE 802.3 annex 31D PFC).
| Address | 31..24 | 23..16 | 15..8 | 7..0 | Reset value |
|---|---|---|---|---|---|
| RBB+0x20 | ctrl | PFC wate | rmark | RW 0x00000000 |
control bits:
| Bit | Function |
|---|---|
| 24 | TX PFC en |
| 25 | RX PFC en |
| 28 | TX PFC req |
| 29 | RX PFC req |