doc: describe timestamp limitations for mlx5

[ upstream commit 1a3709c ]

The ConnectX NIC series hardware provides only 63-bit
wide timestamps. The imposed limitations description
added to documentation.

At the moment there are no affected applications known
or bug reports neither, this is just the declaration
of limitation.

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

doc/guides/nics/mlx5.rst

@@ -227,6 +227,20 @@ Limitations
   - Rx queue with LRO offload enabled, receiving a non-LRO packet, can forward
     it with size limited to max LRO size, not to max RX packet length.
 
+- Timestamps:
+
+  - CQE timestamp field width is limited by hardware to 63 bits, MSB is zero.
+  - In the free-running mode the timestamp counter is reset on power on
+    and 63-bit value provides over 1800 years of uptime till overflow.
+  - In the real-time mode
+    (configurable with ``REAL_TIME_CLOCK_ENABLE`` firmware settings),
+    the timestamp presents the nanoseconds elapsed since 01-Jan-1970,
+    hardware timestamp overflow will happen on 19-Jan-2038
+    (0x80000000 seconds since 01-Jan-1970).
+  - The send scheduling is based on timestamps
+    from the reference "Clock Queue" completions,
+    the scheduled send timestamps should not be specified with non-zero MSB.
+
 Statistics
 ----------
 
@@ -839,6 +853,10 @@ Below are some firmware configurations listed.
 
    FLEX_PARSER_PROFILE_ENABLE=0
 
+- enable realtime timestamp format::
+
+   REAL_TIME_CLOCK_ENABLE=1
+
 Prerequisites
 -------------