Merge pull request #1027 from sifive/dev/paulw/rv64-bare-metal

riscv64: samples: add rv64gc bare-metal sample configuration
crosstool-ng · Sep 26, 2018 · ea1072c · ea1072c
2 parents 49520db + af8da8b
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diff --git a/samples/riscv64-unknown-elf/crosstool.config b/samples/riscv64-unknown-elf/crosstool.config
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+CT_EXPERIMENTAL=y
+CT_ARCH_RISCV=y
+# CT_DEMULTILIB is not set
+CT_ARCH_USE_MMU=y
+CT_ARCH_64=y
+CT_DEBUG_GDB=y
+# CT_GDB_CROSS_PYTHON is not set
diff --git a/samples/riscv64-unknown-elf/reported.by b/samples/riscv64-unknown-elf/reported.by
@@ -0,0 +1,3 @@
+reporter_name="Paul Walmsley <paul.walmsley@sifive.com>"
+reporter_url="https://www.sifive.com/"
+reporter_comment=""