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WAR on index mapping when exact and permissive maps differ #1960

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merged 3 commits into from
Sep 8, 2022

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@shmsong shmsong commented Sep 7, 2022

This is a WAR for this upstream issue:

Very counter-intuitively, in ca maps, exact mapping does not imply permissive mapping. The war included in this PR should be a safe change but it isn't a thorough fix of this issue.

The underlying issue is quite similar to this one even though they ended up hitting different asserts.

As shown in the printout from the repro in this PR:


%kernel {
T2_l[ bS17{( 1 * 1 )} ]
   = T0_g[ bS18{( 1 * 1 )} ];
T3_l[ bS16{( 1 * ( 1 * 1 ) )} ]
   = broadcast( T2_l[ bS17{( 1 * 1 )} ] )
T4_g[ iS14{( i4 * ( 1 * 1 ) )} ]
   = T3_l[ bS16{( 1 * ( 1 * 1 ) )} ]
   + T1_g[ iS20{( i4 * ( 1 * 1 ) )} ];

TransformPrinter : 
T0_g[ bS18{( 1 * 1 )} ]
 root domain : (bS0{1},bS1{1})
  Merge: bS0{1} and bS1{1} -> bS18{( 1 * 1 )}
T2_l[ bS17{( 1 * 1 )} ]
 root domain : (bS5{1},bS6{1})
  Merge: bS5{1} and bS6{1} -> bS17{( 1 * 1 )}
T3_l[ bS16{( 1 * ( 1 * 1 ) )} ]
 root domain : (bS7{1},bS8{1},bS9{1})
  Merge: bS8{1} and bS9{1} -> bS15{( 1 * 1 )}
  Merge: bS7{1} and bS15{( 1 * 1 )} -> bS16{( 1 * ( 1 * 1 ) )}
T1_g[ iS20{( i4 * ( 1 * 1 ) )} ]
 root domain : (iS2{i4},bS3{1},bS4{1})
  Merge: bS3{1} and bS4{1} -> bS19{( 1 * 1 )}
  Merge: iS2{i4} and bS19{( 1 * 1 )} -> iS20{( i4 * ( 1 * 1 ) )}
T4_g[ iS14{( i4 * ( 1 * 1 ) )} ]
 root domain : (iS10{i4},bS11{1},bS12{1})
  Merge: bS11{1} and bS12{1} -> bS13{( 1 * 1 )}
  Merge: iS10{i4} and bS13{( 1 * 1 )} -> iS14{( i4 * ( 1 * 1 ) )}
}

In this example bS17 is exact mapped to bS13 but is not permissive mapped to bS13, which was the part that confused the indexing pass.

Semantically, depending on how we want to define permissive mapping, it might make sense to say all of bS13, iS10, and iS14 permissively mapped to bS17, but we might lose precision and consistency quite quickly once we start to map iterdomains on the same tensordomain to each other. This would be the formalization part that'd need some follow up work.

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@csarofeen csarofeen left a comment

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WAR LGTM, maybe we should file an issue to track the questions on formalization of permissive mapping.

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@naoyam naoyam left a comment

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LGTM as well

@shmsong shmsong merged commit 93505bc into devel Sep 8, 2022
@shmsong shmsong deleted the index_mapping_war branch September 8, 2022 23:46
zasdfgbnm added a commit that referenced this pull request Oct 21, 2022
jjsjann123 added a commit that referenced this pull request Nov 9, 2022
Syncing nvfuser devel branch to upstream master. https://github.com/csarofeen/pytorch/

Codegen changes include:

* codegen improvement:
    i. allow non-root trivial reductions, allow empty/no-op fusion
    ii. fixes vectorization checks and size calculation
    iii. bank conflict handle improvement
    iv. enables transpose scheduler

* misc:
    i. CI tests failure fixes
    ii. cpp tests file clean up
    iii. trivial forwarding supports added in codegen runtime
    iv. added factory methods support in codegen

Commits that's in this PR from the devel branch:

```
7117a7e patching nvfuser conv cudnn test numerics mismatch (#2048)
65af1a4 Inserting sync for redundant parallel types is already done at the (#2023)
6ac74d1 Fix sync map (#2047)
f5bca33 Bank conflict checker improvements (#2032)
d2ca7e3 Minor update on cp.async code generation. (#1901)
d36cf61 Test file cleanup (#2040)
0b8e83f Allow non-root trivial reductions (#2037)
a2dfe40 Fix vectorize size calculation (#2035)
e040676 Use withPredicate to replace setPredicate to maintain Exprs immutable (#2025)
197221b removing ci workflow (#2034)
40e2703 Reduction rand like patch (#2031)
bc77266 Add utility for checking bank conflict of shared memory (#2029)
ddd1cf7 Add back FusionReductionWithTrivialReduction_CUDA (#2030)
fbd97e5 Revert "Cleanup trivial reduction workarounds (#2006)" (#2024)
bca20c1 Cleanup trivial reduction workarounds (#2006)
e4b6585 Trivial forwarding (#1995)
1a0e355 Fix contiguity analysis of predicates to match updated contiguity. (#1991)
a4effa6 Enable output allocation cache (#2010)
35440b7 Patching bn inference (#2016)
0f9f0b4 Add matmul benchmark (#2007)
45045cd Enable tests previously disabled due to an aliasing bug (#2005)
967aa77 Contiguous indexing for View operations (#1990)
a43cb20 Make inlining even more modular (#2004)
dc45835 Test util cleanup (#2003)
3ca21eb More strict validation (#2000)
a7a7d57 Fix build problem (#1999)
fc235b0 Just fixes comments (#1998)
482386c cleanup (#1997)
4cbe0db Improve divisible split detection (#1970)
42ccc52 Minor build fix. (#1996)
fcf8c09 Cleanup of lower_utils.cpp: Isolate out GpuLower usage (#1989)
15f2f6d Move ConcretizedBroadcastDomains to shared_ptr in GpuLower. (#1988)
8f1c7f5 Minor cleanup lower_unroll.cpp (#1994)
1d9858c Minor cleanup (#1992)
f262d9c Add support for uniform RNG (#1986)
eb1dad1 Remove non-const functions, remove GpuLower instance on build, pass in ca_map. (#1987)
634820c Add support for some empty fusion (#1981)
eabe8d8 Segment self mapping fusions (#1954)
e96aacf Enable Transpose operation (#1882)
425dce2 Add a null scheduler that helps segmenting away no-op schedules (#1835)
306d4a6 Fix canScheduleCompileTime check of transpose scheduler (#1969)
b1bd32c Minor fix (#1967)
bd93578 Enable transpose scheduler (#1927)
b7a206e Move scheduler vectorize utilities into their own file (#1959)
d9420e4 View scheduling (#1928)
c668e13 Upstream push ci fixes (#1965)
c40202b Fix dump effective bandwidth (#1962)
93505bc WAR on index mapping when exact and permissive maps differ (#1960)
45e95fd Allow splitting inner-most ID to create virtual innermost ID in transpose scheduler (#1930)
a3ecb33 Improve the comments at the beginning of index_compute.h (#1946)
f7bc341 Remove unused variables (#1955)
df3393a Some cleanup (#1957)
7d1d7c8 TVDomainGuard factory (#1953)
357ba22 Fill allocation with nan on tests (#1956)
8eafc54 Fix detection of unmappable root domains (#1952)
90a51f2 Some indexing cleanups, Add eye support (#1940)
ddc01e4 Exclude unsupported data types (#1951)
992e17c test the groups the same order as they are merged (#1949)
208262b Move detection of self mapping IDs to IterDomainGraph from (#1941)
ac4de38 Merge pull request #1945 from csarofeen/master_merge_0828
6310948 Add full, full_like, zeros, zeros_like, ones, ones_like (#1943)
aab10bc Merge remote-tracking branch 'upstream/viable/strict' into HEAD
4c254c0 Fix arange when step is negative (#1942)
89330aa Tensor factories must set the output shape as its input (#1939)
```

RUN_TORCHBENCH: nvfuser

Differential Revision: [D40869846](https://our.internmc.facebook.com/intern/diff/D40869846)
Pull Request resolved: pytorch#87779
Approved by: https://github.com/davidberard98
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3 participants