Rename ports in seq mem

cucapra · Mar 6, 2024 · 729f8e1 · 729f8e1
1 parent 410d42b
commit 729f8e1
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Showing 6 changed files with 23 additions and 12 deletions.
diff --git a/file-tests/should-futil/fixed-point-multi-cycle.expect b/file-tests/should-futil/fixed-point-multi-cycle.expect
@@ -39,9 +39,10 @@ component main() -> () {
     }
     group upd0<"promotable"=1> {
       d0.addr0 = const0.out;
+      d0.content_en = 1'd1;
       d0.write_en = 1'd1;
       d0.write_data = bin_read1_0.out;
-      upd0[done] = d0.write_done;
+      upd0[done] = d0.done;
     }
   }
   control {

diff --git a/file-tests/should-futil/for-multi-dim.expect b/file-tests/should-futil/for-multi-dim.expect
@@ -42,20 +42,22 @@ component main() -> () {
     }
     group let2<"promotable"=2> {
       A_read0_0.in = A.read_data;
-      A_read0_0.write_en = A.read_done;
+      A_read0_0.write_en = A.done;
       let2[done] = A_read0_0.done;
       A.addr1 = j0.out;
       A.addr0 = i0.out;
+      A.content_en = 1'd1;
       A.read_en = 1'd1;
     }
     group upd0<"promotable"=1> {
       B.addr1 = j0.out;
       B.addr0 = i0.out;
+      B.content_en = 1'd1;
       B.write_en = 1'd1;
       add0.left = A_read0_0.out;
       add0.right = const4.out;
       B.write_data = add0.out;
-      upd0[done] = B.write_done;
+      upd0[done] = B.done;
     }
     group upd1<"promotable"=1> {
       j0.write_en = 1'd1;

diff --git a/file-tests/should-futil/for.expect b/file-tests/should-futil/for.expect
@@ -27,18 +27,20 @@ component main() -> () {
     }
     group let1<"promotable"=2> {
       A_read0_0.in = A.read_data;
-      A_read0_0.write_en = A.read_done;
+      A_read0_0.write_en = A.done;
       let1[done] = A_read0_0.done;
       A.addr0 = i0.out;
+      A.content_en = 1'd1;
       A.read_en = 1'd1;
     }
     group upd0<"promotable"=1> {
       B.addr0 = i0.out;
+      B.content_en = 1'd1;
       B.write_en = 1'd1;
       add0.left = A_read0_0.out;
       add0.right = const2.out;
       B.write_data = add0.out;
-      upd0[done] = B.write_done;
+      upd0[done] = B.done;
     }
     group upd1<"promotable"=1> {
       i0.write_en = 1'd1;

diff --git a/file-tests/should-futil/invoke-with-memories.expect b/file-tests/should-futil/invoke-with-memories.expect
@@ -17,16 +17,18 @@ component mem_copy() -> () {
     }
     group let1<"promotable"=2> {
       src_read0_0.in = src.read_data;
-      src_read0_0.write_en = src.read_done;
+      src_read0_0.write_en = src.done;
       let1[done] = src_read0_0.done;
       src.addr0 = zero_0.out;
+      src.content_en = 1'd1;
       src.read_en = 1'd1;
     }
     group upd0<"promotable"=1> {
       dest.addr0 = zero_0.out;
+      dest.content_en = 1'd1;
       dest.write_en = 1'd1;
       dest.write_data = src_read0_0.out;
-      upd0[done] = dest.write_done;
+      upd0[done] = dest.done;
     }
   }
   control {

diff --git a/file-tests/should-futil/use-plus-equals.expect b/file-tests/should-futil/use-plus-equals.expect
@@ -47,20 +47,22 @@ component use_plus_equals() -> () {
     }
     group let3<"promotable"=2> {
       red_read00.in = x2.read_data;
-      red_read00.write_en = x2.read_done;
+      red_read00.write_en = x2.done;
       let3[done] = red_read00.done;
       x2.addr1 = __j0.out;
       x2.addr0 = __i0.out;
+      x2.content_en = 1'd1;
       x2.read_en = 1'd1;
     }
     group upd0<"promotable"=1> {
       x2.addr1 = __j0.out;
       x2.addr0 = __i0.out;
+      x2.content_en = 1'd1;
       x2.write_en = 1'd1;
       add0.left = red_read00.out;
       add0.right = __x_0.out;
       x2.write_data = add0.out;
-      upd0[done] = x2.write_done;
+      upd0[done] = x2.done;
     }
     group upd1<"promotable"=1> {
       __j0.write_en = 1'd1;

diff --git a/src/main/scala/backends/calyx/Backend.scala b/src/main/scala/backends/calyx/Backend.scala
@@ -644,8 +644,8 @@ private class CalyxBackendHelper {
             )
           )
 
-        val donePortName =
-          if rhsInfo.isDefined then "write_done" else "read_done"
+        val donePortName = "done"
+        val contentEnPortName = "content_en"
 
         // The value is generated on `read_data` and written on `write_data`.
         val portName =
@@ -684,6 +684,8 @@ private class CalyxBackendHelper {
           }
         })
 
+        val contentEnableStruct = List(Assign(ConstantPort(1,1), arr.port(contentEnPortName)))
+
         val readEnPort = if isParam then {
               ThisPort(CompVar(s"${id}_read_en"))
           } else {
@@ -707,7 +709,7 @@ private class CalyxBackendHelper {
         EmitOutput(
           accessPort,
           Some(donePort),
-          (indexing ++ writeEnStruct) ++ readEnStruct,
+          (indexing ++ contentEnableStruct ++ writeEnStruct) ++ readEnStruct,
           delay,
           Some((donePort, delay))
         )