dont generate write_en assignment for reads

cucapra · Feb 16, 2024 · 88e05e5 · 88e05e5
1 parent 22f4e87
commit 88e05e5
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Showing 6 changed files with 10 additions and 14 deletions.
diff --git a/file-tests/should-futil/fixed-point-multi-cycle.expect b/file-tests/should-futil/fixed-point-multi-cycle.expect
@@ -38,9 +38,9 @@ component main() -> () {
       mult_pipe1.go = !mult_pipe1.done ? 1'd1;
     }
     group upd0<"promotable"=1> {
+      d0.content_en = 1'd1;
       d0.addr0 = const0.out;
       d0.write_en = 1'd1;
-      d0.content_en = 1'd1;
       d0.write_data = bin_read1_0.out;
       upd0[done] = d0.done;
     }

diff --git a/file-tests/should-futil/for-multi-dim.expect b/file-tests/should-futil/for-multi-dim.expect
@@ -44,16 +44,15 @@ component main() -> () {
       A_read0_0.in = A.read_data;
       A_read0_0.write_en = A.done;
       let2[done] = A_read0_0.done;
+      A.content_en = 1'd1;
       A.addr1 = j0.out;
       A.addr0 = i0.out;
-      A.write_en = 1'd0;
-      A.content_en = 1'd1;
     }
     group upd0<"promotable"=1> {
+      B.content_en = 1'd1;
       B.addr1 = j0.out;
       B.addr0 = i0.out;
       B.write_en = 1'd1;
-      B.content_en = 1'd1;
       add0.left = A_read0_0.out;
       add0.right = const4.out;
       B.write_data = add0.out;

diff --git a/file-tests/should-futil/for.expect b/file-tests/should-futil/for.expect
@@ -29,14 +29,13 @@ component main() -> () {
       A_read0_0.in = A.read_data;
       A_read0_0.write_en = A.done;
       let1[done] = A_read0_0.done;
-      A.addr0 = i0.out;
-      A.write_en = 1'd0;
       A.content_en = 1'd1;
+      A.addr0 = i0.out;
     }
     group upd0<"promotable"=1> {
+      B.content_en = 1'd1;
       B.addr0 = i0.out;
       B.write_en = 1'd1;
-      B.content_en = 1'd1;
       add0.left = A_read0_0.out;
       add0.right = const2.out;
       B.write_data = add0.out;

diff --git a/file-tests/should-futil/invoke-with-memories.expect b/file-tests/should-futil/invoke-with-memories.expect
@@ -19,14 +19,13 @@ component mem_copy() -> () {
       src_read0_0.in = src.read_data;
       src_read0_0.write_en = src.done;
       let1[done] = src_read0_0.done;
-      src.addr0 = zero_0.out;
-      src.write_en = 1'd0;
       src.content_en = 1'd1;
+      src.addr0 = zero_0.out;
     }
     group upd0<"promotable"=1> {
+      dest.content_en = 1'd1;
       dest.addr0 = zero_0.out;
       dest.write_en = 1'd1;
-      dest.content_en = 1'd1;
       dest.write_data = src_read0_0.out;
       upd0[done] = dest.done;
     }

diff --git a/file-tests/should-futil/use-plus-equals.expect b/file-tests/should-futil/use-plus-equals.expect
@@ -49,16 +49,15 @@ component use_plus_equals() -> () {
       red_read00.in = x2.read_data;
       red_read00.write_en = x2.done;
       let3[done] = red_read00.done;
+      x2.content_en = 1'd1;
       x2.addr1 = __j0.out;
       x2.addr0 = __i0.out;
-      x2.write_en = 1'd0;
-      x2.content_en = 1'd1;
     }
     group upd0<"promotable"=1> {
+      x2.content_en = 1'd1;
       x2.addr1 = __j0.out;
       x2.addr0 = __i0.out;
       x2.write_en = 1'd1;
-      x2.content_en = 1'd1;
       add0.left = red_read00.out;
       add0.right = __x_0.out;
       x2.write_data = add0.out;

diff --git a/src/main/scala/backends/calyx/Backend.scala b/src/main/scala/backends/calyx/Backend.scala
@@ -700,7 +700,7 @@ private class CalyxBackendHelper {
         EmitOutput(
           accessPort,
           Some(donePort),
-          (indexing ++ writeEnStruct) ++ contentEnStruct,
+          contentEnStruct ++ (indexing ++ (if (rhsInfo.isDefined) writeEnStruct else List())),
           delay,
           Some((donePort, delay))
         )