v1.95.3

[Intel]

• [Airmont]
  • Improved the IMC geometry
  • Introducing the Spreadtrum architecture
  • Fixed the Bus and DRAM frequency rates
• [from 11th to 13th gen] Attempt to probe the interleaved controllers
• [Alder Lake/H] Attempt to decode the TCO Watchdog

v1.95.2

[UI]

• Fixed the aggregation of the minimum ratio

[Intel]

• [Airmont][Silvermont] Attempt to decode tCKE from DRMC register
• [Airmont] Improve tWTPr, B2B, tWWDR timings
• [Airmont] Provide a new IMC decoder
• Add the Emerald Rapids architecture entry
• [DDR5][DDR4] Add the RCDw IMC timing
• [Raptor Lake ] De-activate the MSR Uncore counter

[AMD]

• "Zen3/Barcelo-R" and "Zen3+ Rembrandt-R" codenames
• [Zen] Thermal highest limit reset fix

[Misc]

• Code review and Registers documentation:
  AMD HWCR,
  Intel HDC and DRP
  Can build with Intel MSR_ANY_CORE_C0

v1.95.1

• [UI] Split tREFI in two cells in Timing_DDR4
• [UI] Raised the ratio range up to the Uncore max ratio
• [CLI][JSON] Renamed tRCD to tRCD_R and tRCD_W added
• [Intel] Allow ODCM on Raptor Lake [RPL]
• [Intel] RPL: voltage of Pcore, Ecore, System Agent
• [Intel] RPL and ADL Chipset device IDs
• [Intel] Decode the RPL IMC and improve DDR5 support
• [Build] Raise MAX_FREQ_HZ up to 7125000000 Hertz
• [Intel] Mobile {Coffee Lake, Kaby Lake} codenames
• [Intel] Braswell codename detection
• [AMD] SYSCFG Configuration Register
• [AMD] Added EPYC 9654
• [AMD] Transparent SME [TSME]
• [AMD] DRAM Data Scrambling [Scrambler]
• [Doc] Misc Skylake IMC timings specified
• [Doc] Removed cpufreq=0 from README.md