- Xilinx ISE (tested with version 14.7)
git
make
(Linux only)
Since the Saturn board comes with either an LX16 or an LX45, before the "make bin" step, you need to make sure the device in the Makefile is the same as the one you have.
git clone https://github.com/cyrozap/Saturn-UART-Demo.git
cd Saturn-UART-Demo
git submodule update --init
source /opt/Xilinx/14.7/ISE_DS/settings64.sh
make bin
- Clone the repository with your favorite git client
git clone https://github.com/cyrozap/Saturn-UART-Demo.git
- Using your git client, run a submodule update with init
cd Saturn-UART-Demo && git submodule update --init
- Open the Xilinx ISE Project Navigator
- Create a new project (File -> New Project...)
- You can enter anything you want for the name, but the Location and Working Directory must be the same as the folder you just cloned the repository into
- The "Top-level source type" is "HDL"
- Family: Spartan6
- Device: XC6SLX16/XC6SLX45
- Package: CSG324
- Speed: -2
- Preferred Language: Verilog
- Add source files (Project -> Add Source...)
- Select
uart_demo.v
andsaturn.ucf
- Click "OK"
- Select
- Open the properties for the "Generate Programming File" process
- Under "General Options", enable "Create Binary Configuration File"
- Run the "Generate Programming File" process