Merge pull request gem5#71 from OpenXiangShan/fix-se

misc: Fix SE mode. But we don't suggest to use it
cyyself · May 31, 2023 · 7bae8fe · 7bae8fe
2 parents 19891e9 + c1d203b
commit 7bae8fe
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Showing 2 changed files with 9 additions and 2 deletions.
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
@@ -81,7 +81,7 @@ def setCPUClass(options):
         TmpClass = AtomicSimpleCPU
         test_mem_mode = 'atomic'
     # TODO
-    elif options.generic_rv_cpt and options.standard_switch:
+    elif options.standard_switch and hasattr(options, "generic_rv_cpt") and options.generic_rv_cpt:
         CPUClass = TmpClass
         TmpClass = TimingSimpleCPU
 

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
@@ -55,6 +55,7 @@
 #include "mem/packet.hh"
 #include "mem/request.hh"
 #include "params/RiscvISA.hh"
+#include "sim/full_system.hh"
 #include "sim/pseudo_inst.hh"
 
 namespace gem5
@@ -245,7 +246,13 @@ void ISA::clear()
     miscRegFile[MISCREG_VENDORID] = 0;
     miscRegFile[MISCREG_ARCHID] = 0;
     miscRegFile[MISCREG_IMPID] = 0;
-    miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET);
+    if (FullSystem) {
+        // Xiangshan assume machine boots with FS off
+        miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET);
+    } else {
+        // SE assumes process starts with FS on
+        miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET) | (1ULL << FS_OFFSET);
+    }
     miscRegFile[MISCREG_MCOUNTEREN] = 0x7;
     miscRegFile[MISCREG_SCOUNTEREN] = 0x7;
     // don't set it to zero; software may try to determine the supported