mem: Modify SimpleMemory to support vector port

This allows SimpleMemory to be used in a cacheless multiprocessing system to model a "perfect memory". This will also make it easier to write CPU performance tests since there will be fewer variables when testing. Change-Id: I90543b3e010f28b16a2c9f817217ceb3fafbb823 Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
darchr · Aug 23, 2018 · 38d07ab · 38d07ab
1 parent 4679fbd
commit 38d07ab
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Showing 3 changed files with 34 additions and 18 deletions.
diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py
@@ -45,7 +45,7 @@
 class SimpleMemory(AbstractMemory):
     type = 'SimpleMemory'
     cxx_header = "mem/simple_mem.hh"
-    port = SlavePort("Slave ports")
+    port = VectorSlavePort("Slave ports")
     latency = Param.Latency('30ns', "Request to response latency")
     latency_var = Param.Latency('0ns', "Request to response latency variance")
     # The memory bandwidth limit default is set to 12.8GB/s which is

diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
@@ -50,12 +50,15 @@
 
 SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
     AbstractMemory(p),
-    port(name() + ".port", *this), latency(p->latency),
+    latency(p->latency),
     latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
     retryReq(false), retryResp(false),
     releaseEvent([this]{ release(); }, name()),
     dequeueEvent([this]{ dequeue(); }, name())
 {
+    for (int i = 0; i < p->port_port_connection_count; ++i) {
+        ports.emplace_back(name() + csprintf(".port[%d]", i), *this, i);
+    }
 }
 
 void
@@ -65,8 +68,10 @@ SimpleMemory::init()
 
     // allow unconnected memories as this is used in several ruby
     // systems at the moment
-    if (port.isConnected()) {
-        port.sendRangeChange();
+    for (const auto& port : ports) {
+        if (port.isConnected()) {
+            port.sendRangeChange();
+        }
     }
 }
 
@@ -99,7 +104,7 @@ SimpleMemory::recvFunctional(PacketPtr pkt)
 }
 
 bool
-SimpleMemory::recvTimingReq(PacketPtr pkt)
+SimpleMemory::recvTimingReq(PacketPtr pkt, int port_id)
 {
     panic_if(pkt->cacheResponding(), "Should not see packets where cache "
              "is responding");
@@ -169,7 +174,7 @@ SimpleMemory::recvTimingReq(PacketPtr pkt)
 
         // emplace inserts the element before the position pointed to by
         // the iterator, so advance it one step
-        packetQueue.emplace(++i, pkt, when_to_send);
+        packetQueue.emplace(++i, pkt, when_to_send, port_id);
 
         if (!retryResp && !dequeueEvent.scheduled())
             schedule(dequeueEvent, packetQueue.back().tick);
@@ -185,9 +190,8 @@ SimpleMemory::release()
 {
     assert(isBusy);
     isBusy = false;
-    if (retryReq) {
-        retryReq = false;
-        port.sendRetryReq();
+    for (auto& port : ports) {
+        port.trySendRetry();
     }
 }
 
@@ -197,7 +201,7 @@ SimpleMemory::dequeue()
     assert(!packetQueue.empty());
     DeferredPacket deferred_pkt = packetQueue.front();
 
-    retryResp = !port.sendTimingResp(deferred_pkt.pkt);
+    retryResp = !ports[deferred_pkt.portNum].sendTimingResp(deferred_pkt.pkt);
 
     if (!retryResp) {
         packetQueue.pop_front();
@@ -237,7 +241,8 @@ SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
     if (if_name != "port") {
         return MemObject::getSlavePort(if_name, idx);
     } else {
-        return port;
+        assert(idx < ports.size());
+        return ports[idx];
     }
 }
 
@@ -253,8 +258,8 @@ SimpleMemory::drain()
 }
 
 SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
-                                     SimpleMemory& _memory)
-    : SlavePort(_name, &_memory), memory(_memory)
+                                     SimpleMemory& _memory, int port_id)
+    : SlavePort(_name, &_memory), memory(_memory), busy(false), idx(port_id)
 { }
 
 AddrRangeList
@@ -280,7 +285,7 @@ SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 bool
 SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
 {
-    return memory.recvTimingReq(pkt);
+    return memory.recvTimingReq(pkt, idx);
 }
 
 void

diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
@@ -77,8 +77,10 @@ class SimpleMemory : public AbstractMemory
 
         const Tick tick;
         const PacketPtr pkt;
+        const int portNum;
 
-        DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
+        DeferredPacket(PacketPtr _pkt, Tick _tick, int port_num) :
+            tick(_tick), pkt(_pkt), portNum(port_num)
         { }
     };
 
@@ -88,10 +90,19 @@ class SimpleMemory : public AbstractMemory
       private:
 
         SimpleMemory& memory;
+        bool busy;
+        int idx;
 
       public:
 
-        MemoryPort(const std::string& _name, SimpleMemory& _memory);
+        MemoryPort(const std::string& _name, SimpleMemory& _memory, int idx);
+
+        void trySendRetry() {
+            if (busy) {
+                sendRetryReq();
+                busy = false;
+            }
+        }
 
       protected:
 
@@ -107,7 +118,7 @@ class SimpleMemory : public AbstractMemory
 
     };
 
-    MemoryPort port;
+    std::vector<MemoryPort> ports;
 
     /**
      * Latency from that a request is accepted until the response is
@@ -197,7 +208,7 @@ class SimpleMemory : public AbstractMemory
 
     void recvFunctional(PacketPtr pkt);
 
-    bool recvTimingReq(PacketPtr pkt);
+    bool recvTimingReq(PacketPtr pkt, int port_id);
 
     void recvRespRetry();