Mixed Signal Circuit Design and Simulation Marathon: Abstructs

#Reference Circuit Digram Esim

[Verilog_Code]

[software use]( esim ngspice Makerchip Verilator)

#Netlist

#Steps to run generate NgVeri Model`

Open eSim Run NgVeri-Makerchip Add top level verilog file in Makerchip Tab Click on NgVeri tab Add dependency files Click on Run Verilog to NgSpice Converter Debug if any errors Model created successfully

#Steps to run this project

Open a new terminal Clone this project using the following command: git clone https://github.com/das-shounak96/Mix_signal_clock_Divider

Run ngspice: ngspice shounak_clk_div.cir.out To run the project in eSim: Run eSim Load the project Open eeSchema

#Acknowlegdements

IIT Bombay Google.com Skywater OPen Source PDK Tim Edwards, SVP Analog & Platform, Efabless Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - kunalpghosh@gmail.com Fossee Spoken Tutorial MeitY_C2s Sumanto Kar, eSim Team, FOSSEE