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+EmulationCore\PropellerCPU.cs - for PropellerCPU class changed ancestor
to Propeller.DirectMemory and consequences, spelling errors. Now it
compiles well.
+EmulationCore\Cog.cs - changed references of CogSpecialAddress to
Assembly.RegisterAddress, and references of CogConditionCodes to
Assembly.ConditionCodes, using the definitions of
Propeller\AssemblyRegisters.cs & Propeller\Conditions.cs. Also deleted
obsolete definitions of enum CogSpecialAddress and CogConditionCodes.
Corrected spelling errors.
+Propeller\AssemblyRegisters.cs - Added comments from old code in
EmulationCore\Cogs.cs, principally by adding the correction for PAR
register (allowing writes) in PASM.
+GUI\SpinView.cs - Changed invocations of methods Propeller.ReadYYY() &
Propeller.WriteYYY() to Propeller.DirectReadYYY() &
Propeller.DirectWriteYYY(), following the changes in
Propeller\MemoryManager.cs.
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@gatuno1
gatuno1 committed Mar 31, 2015
1 parent 2eb7f4e commit 789b325
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Showing 4 changed files with 94 additions and 164 deletions.
176 changes: 56 additions & 120 deletions Gear/EmulationCore/Cog.cs
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Expand Up @@ -55,70 +55,6 @@ public enum CogRunState
HUB_HUBOP, //!< Waiting to perform hub operation
}

/*
/// @brief %Cog RAM Special Purpose Registers.
///
/// Source: Table 15 - %Cog RAM Special Purpose Registers, %Propeller P8X32A Datasheet V1.4.0.
public enum CogSpecialAddress : uint
{
COGID = 0x1E9, //!< @todo Document enum value CogSpecialAddress.COGID.
INITCOGID = 0x1EF, //!< @todo Document enum value CogSpecialAddress.INITCOGID.
PAR = 0x1F0, //!< Boot Parameter
CNT = 0x1F1, //!< System Counter
INA = 0x1F2, //!< Input States for P31 - P0.
INB = 0x1F3, //!< Input States for P63 - P32.
OUTA = 0x1F4, //!< Output States for P31 - P0.
OUTB = 0x1F5, //!< Output States for P63 - P32.
DIRA = 0x1F6, //!< Direction States for P31 - P0.
DIRB = 0x1F7, //!< Direction States for P63 - P32.
CNTA = 0x1F8, //!< Counter A Control.
CNTB = 0x1F9, //!< Counter B Control.
FRQA = 0x1FA, //!< Counter A Frequency.
FRQB = 0x1FB, //!< Counter B Frequency.
PHSA = 0x1FC, //!< Counter A Phase.
PHSB = 0x1FD, //!< Counter B Phase.
VCFG = 0x1FE, //!< Video Configuration.
VSCL = 0x1FF //!< Video Scale.
}
/// @todo Document enum Gear.EmulationCore.CogConditionCodes
///
public enum CogConditionCodes : uint
{
IF_NEVER = 0x00, //!< Never execute
IF_A = 0x01, //!< if above (!C & !Z)
IF_NC_AND_NZ = 0x01, //!< if C clear and Z clear
IF_NZ_AND_NC = 0x01, //!< if Z clear and C clear
IF_NC_AND_Z = 0x02, //!< if C clear and Z set
IF_Z_AND_NC = 0x02, //!< if C set and Z clear
IF_NC = 0x03, //!< if C clear
IF_AE = 0x03, //!< if above/equal (!C)
IF_NZ_AND_C = 0x04, //!< if Z clear and C set
IF_C_AND_NZ = 0x04, //!< if C set and Z clear
IF_NZ = 0x05, //!< if Z clear
IF_NE = 0x05, //!< if not equal (!Z)
IF_C_NE_Z = 0x06, //!< if C not equal to Z
IF_Z_NE_C = 0x06, //!< if Z not equal to C
IF_NC_OR_NZ = 0x07, //!< if C clear or Z clear
IF_NZ_OR_NC = 0x07, //!< if Z clear or C clear
IF_C_AND_Z = 0x08, //!< if C set and Z set
IF_Z_AND_C = 0x08, //!< if Z set and C set
IF_C_EQ_Z = 0x09, //!< if C equal to Z
IF_Z_EQ_C = 0x09, //!< if Z equal to C
IF_E = 0x0A, //!< if equal (Z)
IF_Z = 0x0A, //!< if Z set
IF_NC_OR_Z = 0x0B, //!< if C clear or Z set
IF_Z_OR_NC = 0x0B, //!< if Z set or C clear
IF_B = 0x0C, //!< if below (C)
IF_C = 0x0C, //!< if C set
IF_NZ_OR_C = 0x0D, //!< if Z clear or C set
IF_C_OR_NZ = 0x0D, //!< if C set or Z clear
IF_Z_OR_C = 0x0E, //!< if Z set or C set
IF_BE = 0x0E, //!< if below/equal (C | Z)
IF_C_OR_Z = 0x0E, //!< if C set or Z set
IF_ALWAYS = 0x0F //!< Always execute
}
*/

/// @todo Document class Gear.EmulationCore.Cog.
///
Expand All @@ -131,7 +67,7 @@ abstract public partial class Cog
protected volatile uint PC; //!< Program Cursor
protected volatile int BreakPointCogCursor; //!< Breakpoint Address

protected int StateCount; //!< Arguement for the current state
protected int StateCount; //!< Argument for the current state
protected CogRunState State; //!< Current COG state
protected CogRunState NextState; //!< Next state COG state

Expand Down Expand Up @@ -165,12 +101,12 @@ public Cog(PropellerCPU host, uint programAddress, uint param, uint frequency, P
BreakPointCogCursor = -1; // Breakpoint disabled

// We are in boot time load
Memory[(int)CogSpecialAddress.PAR] = param;
Memory[(int)Assembly.RegisterAddress.PAR] = param;
State = CogRunState.WAIT_LOAD_PROGRAM;
StateCount = 0;

// Clear the special purpose registers
for (int i = (int)CogSpecialAddress.CNT; i <= 0x1FF; i++)
for (int i = (int)Assembly.RegisterAddress.CNT; i <= 0x1FF; i++)
{
this[i] = 0;
}
Expand All @@ -193,8 +129,8 @@ public ulong OUT
{
get
{
return Memory[(int)CogSpecialAddress.OUTA] |
(Memory[(int)CogSpecialAddress.OUTB] << 32) |
return Memory[(int)Assembly.RegisterAddress.OUTA] |
(Memory[(int)Assembly.RegisterAddress.OUTB] << 32) |
FreqA.Output |
FreqB.Output |
Video.Output;
Expand All @@ -208,7 +144,7 @@ public uint OUTA
{
get
{
return Memory[(int)CogSpecialAddress.OUTA] |
return Memory[(int)Assembly.RegisterAddress.OUTA] |
((uint)FreqA.Output |
(uint)FreqB.Output |
(uint)Video.Output);
Expand All @@ -226,7 +162,7 @@ public uint OUTB
(uint)((FreqA.Output |
FreqB.Output |
Video.Output) >> 32) |
Memory[(int)CogSpecialAddress.OUTB];
Memory[(int)Assembly.RegisterAddress.OUTB];
}
}

Expand All @@ -236,8 +172,8 @@ public ulong DIR
{
get
{
return (Memory[(int)CogSpecialAddress.DIRB] << 32) |
Memory[(int)CogSpecialAddress.DIRA];
return (Memory[(int)Assembly.RegisterAddress.DIRB] << 32) |
Memory[(int)Assembly.RegisterAddress.DIRA];
}
}

Expand All @@ -247,7 +183,7 @@ public uint DIRA
{
get
{
return Memory[(int)CogSpecialAddress.DIRA];
return Memory[(int)Assembly.RegisterAddress.DIRA];
}
}

Expand All @@ -257,7 +193,7 @@ public uint DIRB
{
get
{
return Memory[(int)CogSpecialAddress.DIRB];
return Memory[(int)Assembly.RegisterAddress.DIRB];
}
}

Expand Down Expand Up @@ -322,7 +258,7 @@ public string CogState
{
// show special registers, because their values are in
// variables in Cog object and not in memory array.
if (i >= (int)CogSpecialAddress.PAR)
if (i >= (int)Assembly.RegisterAddress.PAR)
{
return ReadLong((uint)i);
}
Expand All @@ -344,55 +280,55 @@ public string CogState

/// @todo Document method Gear.EmulationCore.Cog.ConditionCompare.
///
public static bool ConditionCompare(CogConditionCodes condition, bool a, bool b)
public static bool ConditionCompare(Assembly.ConditionCodes condition, bool a, bool b)
{
switch (condition)
{
case CogConditionCodes.IF_NEVER:
case Assembly.ConditionCodes.IF_NEVER:
break;
case CogConditionCodes.IF_NZ_AND_NC:
case Assembly.ConditionCodes.IF_NZ_AND_NC:
if (!a && !b) return false;
break;
case CogConditionCodes.IF_NC_AND_Z:
case Assembly.ConditionCodes.IF_NC_AND_Z:
if (a && !b) return false;
break;
case CogConditionCodes.IF_NC:
case Assembly.ConditionCodes.IF_NC:
if (!b) return false;
break;
case CogConditionCodes.IF_C_AND_NZ:
case Assembly.ConditionCodes.IF_C_AND_NZ:
if (!a && b) return false;
break;
case CogConditionCodes.IF_NZ:
case Assembly.ConditionCodes.IF_NZ:
if (!a) return false;
break;
case CogConditionCodes.IF_C_NE_Z:
case Assembly.ConditionCodes.IF_C_NE_Z:
if (a != b) return false;
break;
case CogConditionCodes.IF_NC_OR_NZ:
case Assembly.ConditionCodes.IF_NC_OR_NZ:
if (!a || !b) return false;
break;
case CogConditionCodes.IF_C_AND_Z:
case Assembly.ConditionCodes.IF_C_AND_Z:
if (a && b) return false;
break;
case CogConditionCodes.IF_C_EQ_Z:
case Assembly.ConditionCodes.IF_C_EQ_Z:
if (a == b) return false;
break;
case CogConditionCodes.IF_Z:
case Assembly.ConditionCodes.IF_Z:
if (a) return false;
break;
case CogConditionCodes.IF_NC_OR_Z:
case Assembly.ConditionCodes.IF_NC_OR_Z:
if (a || !b) return false;
break;
case CogConditionCodes.IF_C:
case Assembly.ConditionCodes.IF_C:
if (b) return false;
break;
case CogConditionCodes.IF_C_OR_NZ:
case Assembly.ConditionCodes.IF_C_OR_NZ:
if (!a || b) return false;
break;
case CogConditionCodes.IF_Z_OR_C:
case Assembly.ConditionCodes.IF_Z_OR_C:
if (a || b) return false;
break;
case CogConditionCodes.IF_ALWAYS:
case Assembly.ConditionCodes.IF_ALWAYS:
return false;
}

Expand Down Expand Up @@ -463,30 +399,30 @@ public void StepInstruction()
///
public uint ReadLong(uint address)
{
// values using CogSpecialAddress enum, instead of direct hex values
switch ((CogSpecialAddress)(address & 0x1FF))
// values using Assembly.RegisterAddress enum, instead of direct hex values
switch ((Assembly.RegisterAddress)(address & 0x1FF))
{
case CogSpecialAddress.CNT:
case Assembly.RegisterAddress.CNT:
return Hub.Counter;
case CogSpecialAddress.INA:
case Assembly.RegisterAddress.INA:
return Hub.INA;
case CogSpecialAddress.INB:
case Assembly.RegisterAddress.INB:
return Hub.INB;
case CogSpecialAddress.CNTA:
case Assembly.RegisterAddress.CNTA:
return FreqA.CTR;
case CogSpecialAddress.CNTB:
case Assembly.RegisterAddress.CNTB:
return FreqB.CTR;
case CogSpecialAddress.FRQA:
case Assembly.RegisterAddress.FRQA:
return FreqA.FRQ;
case CogSpecialAddress.FRQB:
case Assembly.RegisterAddress.FRQB:
return FreqB.FRQ;
case CogSpecialAddress.PHSA:
case Assembly.RegisterAddress.PHSA:
return FreqA.PHS;
case CogSpecialAddress.PHSB:
case Assembly.RegisterAddress.PHSB:
return FreqB.PHS;
case CogSpecialAddress.VCFG:
case Assembly.RegisterAddress.VCFG:
return Video.CFG;
case CogSpecialAddress.VSCL:
case Assembly.RegisterAddress.VSCL:
return Video.SCL;
default:
return Memory[address & 0x1FF];
Expand All @@ -507,37 +443,37 @@ public uint ReadLong(uint address)
/// and GEAR didn't emulate that.
protected void WriteLong(uint address, uint data)
{
// values using CogSpecialAddress enum, instead of direct hex values
switch ((CogSpecialAddress)(address & 0x1FF))
// values using Assembly.RegisterAddress enum, instead of direct hex values
switch ((Assembly.RegisterAddress)(address & 0x1FF))
{
// Read only registers
// case CogSpecialAddress.PAR: // PAR register changed to writeable
case CogSpecialAddress.CNT:
case CogSpecialAddress.INA:
case CogSpecialAddress.INB:
// case Assembly.RegisterAddress.PAR: // PAR register changed to writeable
case Assembly.RegisterAddress.CNT:
case Assembly.RegisterAddress.INA:
case Assembly.RegisterAddress.INB:
return;
case CogSpecialAddress.CNTA:
case Assembly.RegisterAddress.CNTA:
FreqA.CTR = data;
break;
case CogSpecialAddress.CNTB:
case Assembly.RegisterAddress.CNTB:
FreqB.CTR = data;
break;
case CogSpecialAddress.FRQA:
case Assembly.RegisterAddress.FRQA:
FreqA.FRQ = data;
break;
case CogSpecialAddress.FRQB:
case Assembly.RegisterAddress.FRQB:
FreqB.FRQ = data;
break;
case CogSpecialAddress.PHSA:
case Assembly.RegisterAddress.PHSA:
FreqA.PHS = data;
break;
case CogSpecialAddress.PHSB:
case Assembly.RegisterAddress.PHSB:
FreqB.PHS = data;
break;
case CogSpecialAddress.VCFG:
case Assembly.RegisterAddress.VCFG:
Video.CFG = data;
break;
case CogSpecialAddress.VSCL:
case Assembly.RegisterAddress.VSCL:
Video.SCL = data;
break;
default:
Expand Down

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