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SyntaxError - invalid character #1

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kassane opened this issue Apr 30, 2022 · 14 comments
Closed

SyntaxError - invalid character #1

kassane opened this issue Apr 30, 2022 · 14 comments

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@kassane
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kassane commented Apr 30, 2022

I obtained an error in phase3.py using the D1-H manual v1.0.

Full log: https://pastebin.com/m7ap8GZP

Output:

# [...]
WARNING:root:'SPI_NDMA_MODE_CTL': Default 17 for field ['7:6', 'R/W ', '0x11 ', 'SPI_ACT_M  SPI NDMA Active Mode \n00: dma_active is low   \n01: dma_active is high \n10: dma_active is controlled by dma_request (DRQ) \n11: dma_active is controlled by controller '] does not fit into slot with bitrange 7:6
WARNING:root:register 'DBI_CTL_0' field 'RGB_SOURCE_FORMAT' enum variants are not unique ([('0000', ' RGB '), ('0001', ' RBG '), ('0010', ' GRB '), ('0011', ' GBR '), ('0100', ' BRG '), ('0101', ' BGR'), ('Others', ' Reserved    When video_source_type is RGB16 (DBI_CTL_0[bit0] = 1) '), ('0000', ' RGB  0001~0100: Reserved '), ('0101', ' BGR '), ('0110', ' GRBG_0 {G[5:3]R[4:0]B[4:0]G[2:0]} '), ('0111', ' GBRG_0 {G[5:3]B[4:0]R[4:0]G[2:0]} '), ('1000', ' GRBG_1 {G[2:0]R[4:0]B[4:0]G[5:3]} '), ('1001', ' GBRG_1 {G[2:0]B[4:0]R[4:0]G[5:3]}  Others: Reserved ')], counter = 2). Giving up.
WARNING:root:register 'DBI_CTL_1' field 'RGB666_FMT' enum variants are not unique ([['00', ' Normal Format '], ['01', ' Special Format for ILITEK '], ['10', ' Special Format for New Vision ']], counter = 3). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': '0 burst' in field 'DBC' in register 'SPI_BCC' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1 burst  …  N: N bursts  Cannot be written when XCH=1' in field 'DBC' in register 'SPI_BCC' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': '0 burst' in field 'STC' in register 'SPI_BCC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': '1 burst  …  N: N bursts  Cannot be written when XCH=1' in field 'STC' in register 'SPI_BCC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': '0 byte in TXFIFO' in field 'TF_CNT' in register 'SPI_FSR' (num_bits = 8)
WARNING:root:Could not interpret enumeratedValue '1': '1 byte in TXFIFO  …' in field 'TF_CNT' in register 'SPI_FSR' (num_bits = 8)
WARNING:root:Could not interpret enumeratedValue '0': '0 byte in RXFIFO' in field 'RF_CNT' in register 'SPI_FSR' (num_bits = 8)
WARNING:root:Could not interpret enumeratedValue '1': '1 byte in RXFIFO  …' in field 'RF_CNT' in register 'SPI_FSR' (num_bits = 8)
WARNING:root:Could not interpret enumeratedValue '0': '0 burst' in field 'MBC' in register 'SPI_MBC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': '1 burst  …  N: N bursts  Cannot be written when XCH=1.' in field 'MBC' in register 'SPI_MBC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': '0 burst' in field 'MWTC' in register 'SPI_MTC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': '1 burst  …  N: N bursts  Cannot be written when XCH=1.' in field 'MWTC' in register 'SPI_MTC' (num_bits = 24)
WARNING:root:register 'SPI_NDMA_MODE_CTL' field 'SPI_ACT_M' enum variants are not unique ([['00', ' dma_active is low   '], ['01', ' dma_active is high '], ['10', ' dma_active is controlled by dma_request (DRQ) '], ['11', ' dma_active is controlled by controller ']], counter = 4). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': 'No wait states inserted  n: n SPI_SCLK wait states inserted  Cannot be written when XCH=1.' in field 'SWC' in register 'SPI_WCR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'No wait states inserted  n: n SPI_SCLK wait states inserted  Cannot be written when XCH=1.' in field 'WCC' in register 'SPI_WCR' (num_bits = 16)
WARNING:root:'DMAC_AUTO_GATE_REG': Invalid field ['When initializing the DMA Controller, the bit[2] should be set up.', '', '', '']: Bitrange error
INFO:root:'DMAC': Register block: None: {'DMAC_AUTO_GATE_REG': [40], 'DMAC_IRQ_EN_REG0': [0], 'DMAC_IRQ_EN_REG1': [4], 'DMAC_IRQ_PEND_REG0': [16], 'DMAC_IRQ_PEND_REG1': [20], 'DMAC_STA_REG': [48]}
INFO:root:'DMAC': Register block: ('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)): {'DMAC_BCNT_LEFT_REGN': [280, 344, 408, 472, 536, 600, 664, 728, 792, 856, 920, 984, 1048, 1112, 1176, 1240], 'DMAC_CFG_REGN': [268, 332, 396, 460, 524, 588, 652, 716, 780, 844, 908, 972, 1036, 1100, 1164, 1228], 'DMAC_CUR_DEST_REGN': [276, 340, 404, 468, 532, 596, 660, 724, 788, 852, 916, 980, 1044, 1108, 1172, 1236], 'DMAC_CUR_SRC_REGN': [272, 336, 400, 464, 528, 592, 656, 720, 784, 848, 912, 976, 1040, 1104, 1168, 1232], 'DMAC_DESC_ADDR_REGN': [264, 328, 392, 456, 520, 584, 648, 712, 776, 840, 904, 968, 1032, 1096, 1160, 1224], 'DMAC_EN_REGN': [256, 320, 384, 448, 512, 576, 640, 704, 768, 832, 896, 960, 1024, 1088, 1152, 1216], 'DMAC_FDESC_ADDR_REGN': [300, 364, 428, 492, 556, 620, 684, 748, 812, 876, 940, 1004, 1068, 1132, 1196, 1260], 'DMAC_MODE_REGN': [296, 360, 424, 488, 552, 616, 680, 744, 808, 872, 936, 1000, 1064, 1128, 1192, 1256], 'DMAC_PARA_REGN': [284, 348, 412, 476, 540, 604, 668, 732, 796, 860, 924, 988, 1052, 1116, 1180, 1244], 'DMAC_PAU_REGN': [260, 324, 388, 452, 516, 580, 644, 708, 772, 836, 900, 964, 1028, 1092, 1156, 1220], 'DMAC_PKG_NUM_REGN': [304, 368, 432, 496, 560, 624, 688, 752, 816, 880, 944, 1008, 1072, 1136, 1200, 1264]}
WARNING:root:Could not interpret enumeratedValue '0': 'Idle' in field 'DMA_STATUS' in register 'DMAC_STA_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1': 'Busy' in field 'DMA_STATUS' in register 'DMAC_STA_REG' (num_bits = 16)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_TX_DMA_LIST' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_RX_DMA_LIST' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_RX_DMA_CUR_BUF' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_RX_DMA_CUR_DESC' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_TX_DMA_CUR_DESC' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_TX_DMA_CUR_BUF' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:'EMAC': Register block: None: {'EMAC_ADDR_HIGH0': [80], 'EMAC_ADDR_LOW0': [84], 'EMAC_BASIC_CTL0': [0], 'EMAC_BASIC_CTL1': [4], 'EMAC_INT_EN': [12], 'EMAC_INT_STA': [8], 'EMAC_MII_CMD': [72], 'EMAC_MII_DATA': [76], 'EMAC_RGMII_STA': [208], 'EMAC_RX_CTL0': [36], 'EMAC_RX_CTL1': [40], 'EMAC_RX_DMA_CUR_BUF': [200], 'EMAC_RX_DMA_CUR_DESC': [196], 'EMAC_RX_DMA_LIST': [52], 'EMAC_RX_DMA_STA': [192], 'EMAC_RX_FRM_FLT': [56], 'EMAC_RX_HASH0': [64], 'EMAC_RX_HASH1': [68], 'EMAC_TX_CTL0': [16], 'EMAC_TX_CTL1': [20], 'EMAC_TX_DMA_CUR_BUF': [184], 'EMAC_TX_DMA_CUR_DESC': [180], 'EMAC_TX_DMA_LIST': [32], 'EMAC_TX_DMA_STA': [176], 'EMAC_TX_FLOW_CTL': [28]}
INFO:root:'EMAC': Register block: ('N', (1, 2, 3, 4, 5, 6, 7)): {'EMAC_ADDR_HIGHN': [88, 96, 104, 112, 120, 128, 136], 'EMAC_ADDR_LOWN': [92, 100, 108, 116, 124, 132, 140]}
WARNING:root:register 'EMAC_RX_FRM_FLT' field 'CTL_FRM_FILTER' enum variants are not unique ([['00', ' Drop all control frames '], ['01', ' Drop all control frames '], ['10', ' Receive all control frames '], ['11', ' Receive all control frames when passing the address filter ']], counter = 5). Giving up.
WARNING:root:[['EMAC ', '0x04500000   ']]: Registers not used in any peripheral: ['EMAC_ADDR_HIGHN', 'EMAC_ADDR_LOWN']
WARNING:root:Could not interpret enumeratedValue '110': 'HS400 speed mode' in field 'CRC_DET_PARA' in register 'SMHC_CSDC' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '011': 'Other speed mode' in field 'CRC_DET_PARA' in register 'SMHC_CSDC' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1x': '8-bit width' in field 'CARD_WID' in register 'SMHC_CTYPE' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue 'Others': 'Reserved  It  should  be  programmed  the  same  as  the  DMA  controller  multiple  transaction  size.  The  units  for  the  transfer  are  the  DWORD.  A  single  transfer  would  be  signaled  based  on  this  value.  The  value  should  be  sub-multiple  of  (RX_TL  +  1)  and  (FIFO_DEPTH - TX_TL)  Recommended:  FIFO_DEPTH = 256, FIFO_SIZE = 256 * 32 = 1K  MSize = 16, TX_TL = 240, RX_TL = 15' in field 'BSIZE_OF_TRANS' in register 'SMHC_FIFOTH' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue 'EBE': 'End Bit Error    RTO: Response Timeout    RCRC: Response CRC    SBE: Start Bit Error    DRTO: Data Read Timeout    DCRC: Data CRC for Receive    RE: Response Error    Writing 1 clears this bit.' in field 'ERR_FLAG_SUM' in register 'SMHC_IDST_REG' (num_bits = 1)
WARNING:root:register 'SMHC_NTSR' field 'CMD_SAMPLE_TIMING_PHASE' enum variants are not unique ([['00', ' Sample timing phase offset 90  '], ['01', ' Sample timing phase offset 180  '], ['10', ' Sample timing phase offset 270  '], ['11', ' Ignore ']], counter = 2). Giving up.
WARNING:root:register 'SMHC_STATUS' field 'FSM_STA' enum variants are not unique ([['0000', ' Idle '], ['0001', ' Send init sequence '], ['0010', ' TX CMD start bit '], ['0011', ' TX CMD TX bit '], ['0100', ' TX CMD index + argument '], ['0101', ' TX CMD CRC7 '], ['0110', ' TX CMD end bit '], ['0111', ' RX response start bit '], ['1000', ' RX response IRQ response '], ['1001', ' RX response TX bit '], ['1010', ' RX response CMD index '], ['1011', ' RX response data '], ['1100', ' RX response CRC7 '], ['1101', ' RX response end bit '], ['1110', ' CMD path wait NCC '], ['1111', ' Wait; CMD-to-response turn around ']], counter = 2). Giving up.
WARNING:root:'LCD_CTL_REG': Field names are not all known; for example the one described by: 'Set the interface type of LCD controller. \n00: HV(Sync+DE) \n01: 8080 I/F \n1x: Reserved '
WARNING:root:Offset is too complicated: 'Offset: 0x002C+N*0x04(N=0 – 3)'
Traceback (most recent call last):
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 1180, in infer_register_instance_structure
    register_offset = eval(spec[len("Offset:"):].strip(), eval_env)
  File "<string>", line 1
    0x002C+N*0x04(N=0 – 3)
                      ^
SyntaxError: invalid character '–' (U+2013)
Traceback (most recent call last):
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 1455, in <module>
    process_register_block(global_registers, svd_registers)
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 1306, in process_register_block
    common_vars_registers, simplified_offsets = infer_register_instance_structure(cluster_visible_registers, x_module_name)
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 1180, in infer_register_instance_structure
    register_offset = eval(spec[len("Offset:"):].strip(), eval_env)
  File "<string>", line 1
    0x002C+N*0x04(N=0 – 3)
                      ^
SyntaxError: invalid character '–' (U+2013)
@kassane kassane mentioned this issue Apr 30, 2022
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@daym
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daym commented May 2, 2022 •
edited

I've pushed a fix to the branch "main", see 82ed374 . Please test!

@kassane
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kassane commented May 2, 2022

I've pushed a fix to the branch "main", see 82ed374 . Please test!

Nice!

Now, I get another error:

# [...]
WARNING:root:'HS_TMR1_CURNT_HI_REG': Invalid field ['HSTimer1 is a 56-bit counter. The current value consists of two parts: HS_TMR1_CUR_VALUE_LO acts as the', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['bit[31', '0]  and  HS_TMR1_CUR_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  current  value,']
WARNING:root:'HS_TMR1_CURNT_HI_REG': Invalid field ['HS_TMR1_CUR_VALUE_LO should be done before HS_TMR1_CUR_VALUE_HI.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR1_INTV_HI_REG': Invalid field ['HSTimer1 is a 56-bit counter. The interval value consists of two parts: HS_TMR1_INTV_VALUE_LO acts as', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['the  bit[31', '0]  and  HS_TMR1_INTV_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  interval  value,']
WARNING:root:'HS_TMR1_INTV_HI_REG': Invalid field ['HS_TMR1_INTV_LO_REG should be done before HS_TMR1_INTV_HI_REG.', '', '', '']: Bitrange error
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD0' in register 'IRQ_MODE0_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD0' in register 'IRQ_MODE0_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD1' in register 'IRQ_MODE1_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD1' in register 'IRQ_MODE1_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD2' in register 'IRQ_MODE2_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD2' in register 'IRQ_MODE2_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD3' in register 'IRQ_MODE3_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD3' in register 'IRQ_MODE3_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD4' in register 'IRQ_MODE4_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD4' in register 'IRQ_MODE4_REG' (num_bits = 32)
Traceback (most recent call last):
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 1086, in <module>
    summary, container = parse_Summary(container, module)
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 1007, in parse_Summary
    for offset in register_summary_instances_guess(offsetspec, part, module):
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 897, in register_summary_instances_guess
    for module_name, module_baseAddress in unroll_Module(module):
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 135, in unroll_Module
    assert header == ["Module_Name", "Base_Address"], header
AssertionError: ['Module_Name', 'Description']
make: *** [Makefile:16: phase3_host.svd] Erro 1

@kassane
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kassane commented May 2, 2022

Test w/ draft v0.1:

WARNING:root:register 'SMHC_NTSR' field 'CMD_SAMPLE_TIMING_PHASE' enum variants are not unique ([['00', ' Sample timing phase offset 90  '], ['01', ' Sample timing phase offset 180  '], ['10', ' Sample timing phase offset 270  '], ['11', ' Ignore ']], counter = 2). Giving up.
WARNING:root:register 'SMHC_STATUS' field 'FSM_STA' enum variants are not unique ([['0000', ' Idle '], ['0001', ' Send init sequence '], ['0010', ' TX CMD start bit '], ['0011', ' TX CMD TX bit '], ['0100', ' TX CMD index + argument '], ['0101', ' TX CMD CRC7 '], ['0110', ' TX CMD end bit '], ['0111', ' RX response start bit '], ['1000', ' RX response IRQ response '], ['1001', ' RX response TX bit '], ['1010', ' RX response CMD index '], ['1011', ' RX response data '], ['1100', ' RX response CRC7 '], ['1101', ' RX response end bit '], ['1110', ' CMD path wait NCC '], ['1111', ' Wait; CMD-to-response turn around ']], counter = 2). Giving up.
WARNING:root:'LCD_CTL_REG': Field names are not all known; for example the one described by: 'Set the interface type of LCD controller. \n00: HV(Sync+DE) \n01: 8080 I/F \n1x: Reserved '
INFO:root:'TCON_LCD0': Register block: None: {'FSYNC_GEN_CTRL_REG': [552], 'FSYNC_GEN_DLY_REG': [556], 'LCD_3D_FIFO_REG': [60], 'LCD_BASIC0_REG': [72], 'LCD_BASIC1_REG': [76], 'LCD_BASIC2_REG': [80], 'LCD_BASIC3_REG': [84], 'LCD_CEU_CTL_REG': [256], 'LCD_CMAP_CTL_REG': [384], 'LCD_CMAP_EVEN0_REG': [408], 'LCD_CMAP_EVEN1_REG': [412], 'LCD_CMAP_ODD0_REG': [400], 'LCD_CMAP_ODD1_REG': [404], 'LCD_CPU_IF_REG': [96], 'LCD_CPU_RD0_REG': [104], 'LCD_CPU_RD1_REG': [108], 'LCD_CPU_TRI0_REG': [352], 'LCD_CPU_TRI1_REG': [356], 'LCD_CPU_TRI2_REG': [360], 'LCD_CPU_TRI3_REG': [364], 'LCD_CPU_TRI4_REG': [368], 'LCD_CPU_TRI5_REG': [372], 'LCD_CPU_WR_REG': [100], 'LCD_CTL_REG': [64], 'LCD_DCLK_REG': [68], 'LCD_DEBUG_REG': [252], 'LCD_FRM_CTL_REG': [16], 'LCD_GCTL_REG': [0], 'LCD_GINT0_REG': [4], 'LCD_GINT1_REG': [8], 'LCD_HV_IF_REG': [88], 'LCD_IO_POL_REG': [136], 'LCD_IO_TRI_REG': [140], 'LCD_LVDS1_IF_REG': [580], 'LCD_LVDS_ANA0_REG': [544], 'LCD_LVDS_IF_REG': [132], 'LCD_SAFE_PERIOD_REG': [496], 'LCD_SLAVE_STOP_POS_REG': [568], 'LCD_SYNC_CTL_REG': [560], 'LCD_SYNC_POS_REG': [564]}
INFO:root:'TCON_LCD0': Register block: ('N', (0, 1, 2)): {'LCD_CEU_COEF_ADD_REG': [284, 300, 316], 'LCD_CEU_COEF_RANG_REG': [320, 324, 328]}
INFO:root:'TCON_LCD0': Register block: ('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)): {'LCD_CEU_COEF_MUL_REG': [272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312]}
INFO:root:'TCON_LCD0': Register block: ('N', (0, 1, 2, 3)): {'LCD_FRM_TAB_REG': [44, 48, 52, 56]}
INFO:root:'TCON_LCD0': Register block: ('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255)): {'LCD_GAMMA_TABLE_REG': [1024, 1028, 1032, 1036, 1040, 1044, 1048, 1052, 1056, 1060, 1064, 1068, 1072, 1076, 1080, 1084, 1088, 1092, 1096, 1100, 1104, 1108, 1112, 1116, 1120, 1124, 1128, 1132, 1136, 1140, 1144, 1148, 1152, 1156, 1160, 1164, 1168, 1172, 1176, 1180, 1184, 1188, 1192, 1196, 1200, 1204, 1208, 1212, 1216, 1220, 1224, 1228, 1232, 1236, 1240, 1244, 1248, 1252, 1256, 1260, 1264, 1268, 1272, 1276, 1280, 1284, 1288, 1292, 1296, 1300, 1304, 1308, 1312, 1316, 1320, 1324, 1328, 1332, 1336, 1340, 1344, 1348, 1352, 1356, 1360, 1364, 1368, 1372, 1376, 1380, 1384, 1388, 1392, 1396, 1400, 1404, 1408, 1412, 1416, 1420, 1424, 1428, 1432, 1436, 1440, 1444, 1448, 1452, 1456, 1460, 1464, 1468, 1472, 1476, 1480, 1484, 1488, 1492, 1496, 1500, 1504, 1508, 1512, 1516, 1520, 1524, 1528, 1532, 1536, 1540, 1544, 1548, 1552, 1556, 1560, 1564, 1568, 1572, 1576, 1580, 1584, 1588, 1592, 1596, 1600, 1604, 1608, 1612, 1616, 1620, 1624, 1628, 1632, 1636, 1640, 1644, 1648, 1652, 1656, 1660, 1664, 1668, 1672, 1676, 1680, 1684, 1688, 1692, 1696, 1700, 1704, 1708, 1712, 1716, 1720, 1724, 1728, 1732, 1736, 1740, 1744, 1748, 1752, 1756, 1760, 1764, 1768, 1772, 1776, 1780, 1784, 1788, 1792, 1796, 1800, 1804, 1808, 1812, 1816, 1820, 1824, 1828, 1832, 1836, 1840, 1844, 1848, 1852, 1856, 1860, 1864, 1868, 1872, 1876, 1880, 1884, 1888, 1892, 1896, 1900, 1904, 1908, 1912, 1916, 1920, 1924, 1928, 1932, 1936, 1940, 1944, 1948, 1952, 1956, 1960, 1964, 1968, 1972, 1976, 1980, 1984, 1988, 1992, 1996, 2000, 2004, 2008, 2012, 2016, 2020, 2024, 2028, 2032, 2036, 2040, 2044]}
INFO:root:'TCON_LCD0': Register block: ('N', (0, 1, 2, 3, 4, 5)): {'xNx': [20, 24, 28, 32, 36, 40]}
WARNING:root:register 'LCD_3D_FIFO_REG' field '3D_FIFO' enum variants are not unique ([['00', ' Bypass '], ['01', ' Used as normal FIFO '], ['10', ' Used as 3D interlace FIFO '], ['11', ' Reserved   ']], counter = 2). Giving up.
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue 'xxx1': '24-bit for DSI' in field 'CPU_MODE' in register 'LCD_CPU_IF_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0x': 'Auto' in field 'SYNC_MODE' in register 'LCD_CPU_TRI2_REG'
WARNING:root:register 'LCD_CPU_TRI3_REG' field 'TRI_INT_MODE' enum variants are not unique ([['00', ' Disable '], ['01', ' Counter mode   '], ['10', ' Te rising mode '], ['11', ' Te falling mode ']], counter = 2). Giving up.
WARNING:root:register 'LCD_CTL_REG' field 'LCD_SRC_SEL' enum variants are not unique ([['000', ' DE '], ['001', ' Color Check '], ['010', ' Grayscale Check '], ['011', ' Black by White Check '], ['100', ' Test Data all 0 '], ['101', ' Test Data all 1 '], ['110', ' Reversed '], ['111', ' Gridding Check       ']], counter = 2). Giving up.
WARNING:root:register 'LCD_DCLK_REG' field 'LCD_DCLK_EN' enum variants are not unique ([('0000', ' dclk_en = 0; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 0;                           '), ('0001', ' dclk_en = 1; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 0;                         '), ('0010', ' dclk_en = 1; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 1;                         '), ('0011', ' dclk_en = 1; dclk1_en = 1; dclk2_en = 0; dclkm2_en = 0;                         '), ('0101', ' dclk_en = 1; dclk1_en = 0; dclk2_en = 1; dclkm2_en = 0;                         '), ('1111', ' dclk_en = 1; dclk1_en = 1; dclk2_en = 1; dclkm2_en = 1;  '), ('Others', 'Reversed ')], counter = 2). Giving up.
WARNING:root:register 'LCD_FRM_CTL_REG' field 'LCD_FRM_TEST' enum variants are not unique ([['00', ' FRM '], ['01', ' Half 5-/6-bit, half FRM '], ['10', ' Half 8-bit, half FRM '], ['11', ' Half 8-bit, half 5-/6-bit   ']], counter = 2). Giving up.
WARNING:root:register 'LCD_HV_IF_REG' field 'RGB888_ODD_ORDER' enum variants are not unique ([['00', ' R→G→B '], ['01', ' B→R→G '], ['10', ' G→B→R '], ['11', ' R→G→B ']], counter = 2). Giving up.
WARNING:root:register 'LCD_HV_IF_REG' field 'RGB888_EVEN_ORDER' enum variants are not unique ([['00', ' R→G→B '], ['01', ' B→R→G '], ['10', ' G→B→R '], ['11', ' R→G→B ']], counter = 2). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': 'Normal polarity' in field 'DATA_INV' in register 'LCD_IO_POL_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': 'Invert the specify output' in field 'DATA_INV' in register 'LCD_IO_POL_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': 'Disable' in field 'DATA_OUTPUT_TRI_EN' in register 'LCD_IO_TRI_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': 'Enable' in field 'DATA_OUTPUT_TRI_EN' in register 'LCD_IO_TRI_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': 'Reverse' in field 'LCD_LVDS_DATA_POL' in register 'LCD_LVDS1_IF_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Normal' in field 'LCD_LVDS_DATA_POL' in register 'LCD_LVDS1_IF_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'Disable' in field 'LVDS_HPREN_DRV' in register 'LCD_LVDS_ANA0_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Enable' in field 'LVDS_HPREN_DRV' in register 'LCD_LVDS_ANA0_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'Normal' in field 'LVDS_REG_PLR' in register 'LCD_LVDS_ANA0_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Reverse' in field 'LVDS_REG_PLR' in register 'LCD_LVDS_ANA0_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'Reverse' in field 'LCD_LVDS_DATA_POL' in register 'LCD_LVDS_IF_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Normal' in field 'LCD_LVDS_DATA_POL' in register 'LCD_LVDS_IF_REG' (num_bits = 4)
WARNING:root:register 'LCD_SAFE_PERIOD_REG' field 'SAFE_PERIOD_MODE' enum variants are not unique ([['000', ' unsafe '], ['001', ' safe '], ['010', ' safe at FIFO_CURR_NUM > SAFE_PERIOD_FIFO_NUM '], ['011', ' safe at 2 and safe at sync active '], ['100', ' safe at line   ']], counter = 2). Giving up.
WARNING:root:'GP_CTRL': Invalid field ['31:24  R/', 'W', '0x0   ', 'ADC_FIRST_DLY  ADC First Convert Delay Setting  ADC conversion of each channel is delayed by N samples. ']: Bitrange error
WARNING:root:'HS_TMR0_CURNT_HI_REG': Invalid field ['HSTimer0 is a 56-bit counter. The current value consists of two parts: HS_TMR0_CUR_VALUE_LO acts as the', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['bit[31', '0]  and  HS_TMR0_CUR_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  current  value,']
WARNING:root:'HS_TMR0_CURNT_HI_REG': Invalid field ['HS_TMR0_CUR_VALUE_LO should be done before HS_TMR0_CUR_VALUE_HI.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR0_INTV_HI_REG': Invalid field ['HSTimer0 is a 56-bit counter. The interval value consists of two parts: HS_TMR0_INTV_VALUE_LO acts as', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['the  bit[31', '0]  and  HS_TMR0_INTV_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  interval  value,']
WARNING:root:'HS_TMR0_INTV_HI_REG': Invalid field ['HS_TMR0_INTV_LO_REG should be done before HS_TMR0_INTV_HI_REG.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR1_CURNT_HI_REG': Invalid field ['HSTimer1 is a 56-bit counter. The current value consists of two parts: HS_TMR1_CUR_VALUE_LO acts as the', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['bit[31', '0]  and  HS_TMR1_CUR_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  current  value,']
WARNING:root:'HS_TMR1_CURNT_HI_REG': Invalid field ['HS_TMR1_CUR_VALUE_LO should be done before HS_TMR1_CUR_VALUE_HI.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR1_INTV_HI_REG': Invalid field ['HSTimer1 is a 56-bit counter. The interval value consists of two parts: HS_TMR1_INTV_VALUE_LO acts as', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['the  bit[31', '0]  and  HS_TMR1_INTV_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  interval  value,']
WARNING:root:'HS_TMR1_INTV_HI_REG': Invalid field ['HS_TMR1_INTV_LO_REG should be done before HS_TMR1_INTV_HI_REG.', '', '', '']: Bitrange error
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD0' in register 'IRQ_MODE0_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD0' in register 'IRQ_MODE0_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD1' in register 'IRQ_MODE1_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD1' in register 'IRQ_MODE1_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD2' in register 'IRQ_MODE2_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD2' in register 'IRQ_MODE2_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD3' in register 'IRQ_MODE3_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD3' in register 'IRQ_MODE3_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD4' in register 'IRQ_MODE4_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD4' in register 'IRQ_MODE4_REG' (num_bits = 32)
INFO:root:'LEDC': Register block: None: {'LEDC_CTRL_REG': [0], 'LEDC_DATA_FINISH_CNT_REG': [8], 'LEDC_DATA_REG': [20], 'LEDC_DMA_CTRL_REG': [24], 'LEDC_INTERRUPT_CTRL_REG': [28], 'LEDC_INT_STS_REG': [32], 'LEDC_WAIT_TIME0_CTRL_REG': [16], 'LEDC_WAIT_TIME1_CTRL_REG': [40], 'LED_RESET_TIMING_CTRL_REG': [12], 'LED_T01_TIMING_CTRL_REG': [4]}
INFO:root:'LEDC': Register block: ('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)): {'LEDC_FIFO_DATA_X': [48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172]}
WARNING:root:Offset is too complicated: 'Offset: 0x0050+N*0x0100+P*0x0004'
Traceback (most recent call last):
  File "/home/kassane/Documentos/allwinner-register-interface-extractor/phase3.py", line 1180, in infer_register_instance_structure
    register_offset = eval(spec[len("Offset:"):].strip(), eval_env)
  File "<string>", line 1, in <module>
NameError: name 'P' is not defined
Traceback (most recent call last):
  File "/home/kassane/Documentos/allwinner-register-interface-extractor/phase3.py", line 1455, in <module>
    process_register_block(global_registers, svd_registers)
  File "/home/kassane/Documentos/allwinner-register-interface-extractor/phase3.py", line 1306, in process_register_block
    common_vars_registers, simplified_offsets = infer_register_instance_structure(cluster_visible_registers, x_module_name)
  File "/home/kassane/Documentos/allwinner-register-interface-extractor/phase3.py", line 1180, in infer_register_instance_structure
    register_offset = eval(spec[len("Offset:"):].strip(), eval_env)
  File "<string>", line 1, in <module>
NameError: name 'P' is not defined
make: *** [Makefile:16: phase3_host.svd] Error 1

@daym
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daym commented May 2, 2022 •
edited

Yeah, that's unfortunate.

Please try adding this:

index 2678884..e34ab88 100644
--- a/phase3.py
+++ b/phase3.py
@@ -1177,6 +1177,7 @@ for module in root_dnode.children:
                       eval_env["N"] = N
                       eval_env["n"] = N
                       eval_env["x"] = N # FIXME remove?
+                      eval_env["P"] = N # FIXME remove?
                       register_offset = eval(spec[len("Offset:"):].strip(), eval_env)
                       common_vars_registers[key][register.name].append(register_offset)
               else:

But make sure you manually check and rewrite the generated sections for registers which use P= in the PDF.

What is going on here is that Allwinner uses equations like 0x123 + N * 4 + P * 100. The extractor cannot interpret that (more than one variable at the same time) correctly (i.e. as a 2 dimensional register array). As far as I know it's only affecting one register block (MSGBOX), so I always manually edit that generated file section.

That's obviously not ideal--ideas welcome. (I'm leaning towards using some kind of xml tree-shape patcher--if that exists)

@kassane kassane mentioned this issue May 2, 2022
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kassane commented May 2, 2022

Ok. But

INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_WADDRL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_WADDRH' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_LMT' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_IS' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_SADDRH' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_CTRL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_FCC' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_SADDRL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_RADDRL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_BL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_STA' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
svd2rust --target "riscv" -i phase3_host.svd
[INFO  svd2rust] Parsing device from SVD file
[INFO  svd2rust] Rendering device
[ERROR svd2rust] Error rendering device
    
    Caused by:
        0: Rendering error at peripheral
           Name: RISCV PLIC
           Description: RISCV PLIC
           Group: generic
        1: Could not expand register or cluster block
        2: Error expanding register
           Name: PLIC_PRIO_REGn_%s
           Description: PLIC_PRIO_REGn_%s
        3: syn error occured
        4: Error converting info name PLIC_PRIO_REGn_%s
        5: Determining syn::TypePath from ident "crate::Reg<plic_prio_regn_%s::PLIC_PRIO_REGN_%S_SPEC>" failed
        6: expected `,`
make: *** [Makefile:19: lib.rs] Erro 1

@daym
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daym commented May 2, 2022 •
edited 

    summary, container = parse_Summary(container, module)
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 1007, in parse_Summary
    for offset in register_summary_instances_guess(offsetspec, part, module):
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 897, in register_summary_instances_guess
    for module_name, module_baseAddress in unroll_Module(module):
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 135, in unroll_Module
    assert header == ["Module_Name", "Base_Address"], header
AssertionError: ['Module_Name', 'Description']
make: *** [Makefile:16: phase3_host.svd] Erro 1

That means it was ready to unroll a module, but it was missing a base address for the module (in the table of the module in the PDF--the one that comes before the register summary and then the individual registers). That's weird. How is one supposed to use that module then, with no address?!

Do you have a link to the PDF for me?

You can edit the part of the assertion so that it tells you more details, for example put this:

 assert header == ["Module_Name", "Base_Address"], module

@daym
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daym commented May 2, 2022 •
edited 

PLIC_PRIO_REG

You can search for PLIC_PRIO_REG in the generated svd. Does it look OK?

I think it's because it's not emitting the <dim> and <dimIncrement> for it, but is using the %s. Can you try adding it manually?

<dim>256</dim> and <dimIncrement>4</dimIncrement>

Not sure why it's not emitting that. Is there a warning or error emitted? grep -i PLIC_PRIO_reg helps there...

@kassane
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kassane commented May 2, 2022 

    summary, container = parse_Summary(container, module)
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 1007, in parse_Summary
    for offset in register_summary_instances_guess(offsetspec, part, module):
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 897, in register_summary_instances_guess
    for module_name, module_baseAddress in unroll_Module(module):
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 135, in unroll_Module
    assert header == ["Module_Name", "Base_Address"], header
AssertionError: ['Module_Name', 'Description']
make: *** [Makefile:16: phase3_host.svd] Erro 1

That means it was ready to unroll a module, but it was missing a base address for the module (in the table of the module in the PDF--the one that comes before the register summary and then the individual registers). That's weird. How is one supposed to use that module then, with no address?!

Do you have a link to the PDF for me?

You can edit the part of the assertion so that it tells you more details, for example put this:

 assert header == ["Module_Name", "Base_Address"], module

Manual_V1.0.tar.gz

Assert removed:

WARNING:root:Field could not be parsed as a bitrange: ['the  bit[31', '0]  and  HS_TMR0_INTV_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  interval  value,']
WARNING:root:'HS_TMR0_INTV_HI_REG': Invalid field ['HS_TMR0_INTV_LO_REG should be done before HS_TMR0_INTV_HI_REG.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR1_CURNT_HI_REG': Invalid field ['HSTimer1 is a 56-bit counter. The current value consists of two parts: HS_TMR1_CUR_VALUE_LO acts as the', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['bit[31', '0]  and  HS_TMR1_CUR_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  current  value,']
WARNING:root:'HS_TMR1_CURNT_HI_REG': Invalid field ['HS_TMR1_CUR_VALUE_LO should be done before HS_TMR1_CUR_VALUE_HI.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR1_INTV_HI_REG': Invalid field ['HSTimer1 is a 56-bit counter. The interval value consists of two parts: HS_TMR1_INTV_VALUE_LO acts as', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['the  bit[31', '0]  and  HS_TMR1_INTV_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  interval  value,']
WARNING:root:'HS_TMR1_INTV_HI_REG': Invalid field ['HS_TMR1_INTV_LO_REG should be done before HS_TMR1_INTV_HI_REG.', '', '', '']: Bitrange error
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD0' in register 'IRQ_MODE0_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD0' in register 'IRQ_MODE0_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD1' in register 'IRQ_MODE1_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD1' in register 'IRQ_MODE1_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD2' in register 'IRQ_MODE2_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD2' in register 'IRQ_MODE2_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD3' in register 'IRQ_MODE3_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD3' in register 'IRQ_MODE3_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD4' in register 'IRQ_MODE4_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD4' in register 'IRQ_MODE4_REG' (num_bits = 32)
Traceback (most recent call last):
  File "/home/kassane/Documentos/allwinner-register-interface-extractor/phase3.py", line 1086, in <module>
    summary, container = parse_Summary(container, module)
  File "/home/kassane/Documentos/allwinner-register-interface-extractor/phase3.py", line 1007, in parse_Summary
    for offset in register_summary_instances_guess(offsetspec, part, module):
  File "/home/kassane/Documentos/allwinner-register-interface-extractor/phase3.py", line 897, in register_summary_instances_guess
    for module_name, module_baseAddress in unroll_Module(module):
  File "/home/kassane/Documentos/allwinner-register-interface-extractor/phase3.py", line 145, in unroll_Module
    Base_Address = eval(Base_Address.strip(), {})
  File "<string>", line 1
    FIFO overflow interrupt.  The  data  written  by  external  is  more  than  the  maximum  storage  space of LED FIFO, the LEDC will be in data loss state. At this time,  software needs to deal with the abnormal situation. The processing  mode is as follows.  The software can query LED_FIFO_DATA_REG to determine which  data  has  been  stored  in  the  internal  FIFO  of  LEDC.  The  LEDC  performs soft_reset operation to refresh all data.
         ^^^^^^^^
SyntaxError: invalid syntax
make: *** [Makefile:16: phase3_host.svd] Erro 1

@kassane
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kassane commented May 2, 2022 •
edited 

PLIC_PRIO_REG

You can search for PLIC_PRIO_REG in the generated svd. Does it look OK?

I think it's because it's not emitting the <dim> and <dimIncrement> for it, but is using the %s. Can you try adding it manually?

<dim>256</dim> and <dimIncrement>4</dimIncrement>

Not sure why it's not emitting that. Is there a warning or error emitted? grep -i PLIC_PRIO_reg helps there...

This? [Draft v0.1]

<register>
          <name>PLIC_PRIO_REGn_%s</name>
          <description>PLIC_PRIO_REGn_%s</description>
          <addressOffset>0x4</addressOffset>
          <resetValue>0x0</resetValue>
          <resetMask>0x1</resetMask>
          <fields>
            <field>
              <name>PLIC_PRIO</name>
              <description>PLIC Priority  Support for 32 different levels of priority.  Where, a priority sets to 0 indicates that the interrupt is invalid.  Machine  mode  interrupts  have  unconditionally  higher  priority  than super-user mode interrupts. When the interrupt target mode  is  the  same,  priority  1  is  the  lowest  priority,  priority  31  is  the  highest priority. When multiple interrupts of the same priority are  waiting  arbitration,  the  interrupt  source  ID  is  compared.  The  smaller ID has the higher priority.   </description>
              <bitRange>[0:0]</bitRange>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>

@daym
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daym commented May 2, 2022

Yeah, <dim> and <dimIncrement> are missing.

@daym
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daym commented May 2, 2022

Manual_V1.0.tar.gz

Thanks!

Assert removed:

Well, that's not gonna end well. The assert is documenting preconditions that the following part has to have. And indeed, by removing it, it will fail when trying to get the base address.

You can change the assertion message to tell you module and thus pinpoint where in the PDF they messed up and forgot the base address.

@daym
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daym commented May 2, 2022 •
edited 

    summary, container = parse_Summary(container, module)
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 1007, in parse_Summary
    for offset in register_summary_instances_guess(offsetspec, part, module):
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 897, in register_summary_instances_guess
    for module_name, module_baseAddress in unroll_Module(module):
  File "/home/kassane/Vídeos/nezha/allwinner-register-interface-extractor/phase3.py", line 135, in unroll_Module
    assert header == ["Module_Name", "Base_Address"], header
AssertionError: ['Module_Name', 'Description']
make: *** [Makefile:16: phase3_host.svd] Erro 1

That means it was ready to unroll a module, but it was missing a base address for the module (in the table of the module in the PDF--the one that comes before the register summary and then the individual registers). That's weird. How is one supposed to use that module then, with no address?!

Do you have a link to the PDF for me?

You can edit the part of the assertion so that it tells you more details, for example put this:

 assert header == ["Module_Name", "Base_Address"], module

It's 9.12.3.11 LEDC Interrupt in their PDF. Sigh...

As a workaround, after the failure, you can search for FIFO_OVERFLOW_INT in phase2_result.py and change the header there from ["Module Name ", "Description"] to something else (like ["Interrupt Name", "Description"]. Then, run make again (it will continue with your edited file).

I tried it, phase3 runs to completion then.

I've fixed a small bug in extract.py (in the CPU architecture detection)--now svd2rust, too, will run to completion for D1-H. Please pull from main.

@daym
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daym commented May 2, 2022 •
edited 

PLIC_PRIO_REGn_%s

Filed issue #2 here and fixed it in main branch. It should work now.

@kassane
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kassane commented May 2, 2022

Well done! Works, svd version 1.0 was generated and svd2rust read it without error.

@kassane kassane closed this as completed May 2, 2022
@kassane kassane mentioned this issue Aug 13, 2022
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