svd2rust fails at PLIC_PRIO_REGn_%s for Allwinner D1

[daym]

INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_WADDRL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_WADDRH' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_LMT' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_IS' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_SADDRH' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_CTRL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_FCC' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_SADDRL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_RADDRL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_BL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_STA' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
svd2rust --target "riscv" -i phase3_host.svd
[INFO  svd2rust] Parsing device from SVD file
[INFO  svd2rust] Rendering device
[ERROR svd2rust] Error rendering device
    
    Caused by:
        0: Rendering error at peripheral
           Name: RISCV PLIC
           Description: RISCV PLIC
           Group: generic
        1: Could not expand register or cluster block
        2: Error expanding register
           Name: PLIC_PRIO_REGn_%s
           Description: PLIC_PRIO_REGn_%s
        3: syn error occured
        4: Error converting info name PLIC_PRIO_REGn_%s
        5: Determining syn::TypePath from ident "crate::Reg<plic_prio_regn_%s::PLIC_PRIO_REGN_%S_SPEC>" failed
        6: expected `,`
make: *** [Makefile:19: lib.rs] Erro 1

[daym]

The reason is that PLIC_PRIO_REGn_%s starts with index (!) 1, and that case was broken. Fixed in commit 880ff26.