add tb_same_sim_all_pass_nonzero

vunit/test/acceptance/artificial/vhdl/tb_same_sim_all_pass_nonzero.vhd

@@ -0,0 +1,40 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2019, Lars Asplund lars.anders.asplund@gmail.com
+
+library vunit_lib;
+context vunit_lib.vunit_context;
+
+entity tb_same_sim_all_pass_nonzero is
+  generic (
+    output_path : string;
+    runner_cfg : string);
+end entity;
+
+architecture vunit_test_bench of tb_same_sim_all_pass_nonzero is
+begin
+  test_runner : process
+    variable counter : integer := 1;
+  begin
+    test_runner_setup(runner, runner_cfg);
+    while test_suite loop
+      if run("Test 1") then
+        wait for 10 ns;
+        report "Test 1";
+        assert counter = 1;
+        counter := counter + 1;
+      elsif run("Test 2") then
+        wait for 10 ns;
+        report "Test 2";
+        assert counter = 2;
+        counter := counter + 1;
+      end if;
+    end loop;
+    vunit_lib.runner_pkg.p_disable_simulation_exit(runner_state);
+    test_runner_cleanup(runner);
+    assert false severity error;
+    wait;
+  end process;
+end architecture;

vunit/test/acceptance/test_artificial.py

@@ -117,6 +117,14 @@ def _test_run_selected_tests_in_same_sim_test_bench(self, run_file):
             ("failed", "lib.tb_same_sim_some_fail.Test 2"),
             ("skipped", "lib.tb_same_sim_some_fail.Test 3")])
 
+        self.check(run_file,
+                   exit_code=1,
+                   clean=False,
+                   args=["*same_sim_all_pass_nonzero*Test 1*", "*same_sim_all_pass_nonzero*Test 2*"])
+        check_report(self.report_file, [
+            ("failed", "lib.tb_same_sim_all_pass_nonzero.Test 1"),
+            ("failed", "lib.tb_same_sim_all_pass_nonzero.Test 2")])
+
     @unittest.skipUnless(simulator_is("modelsim"), "Only modelsim supports verilog")
     def test_artificial_verilog(self):
         self.check(self.artificial_run_verilog,
@@ -201,6 +209,9 @@ def test_exit_0_flag(self):
     ("failed", "lib.tb_same_sim_some_fail.Test 2"),
     ("skipped", "lib.tb_same_sim_some_fail.Test 3"),
 
+    ("failed", "lib.tb_same_sim_all_pass_nonzero.Test 1"),
+    ("failed", "lib.tb_same_sim_all_pass_nonzero.Test 2"),
+
     ("passed", "lib.tb_with_checks.Test passing check"),
     ("failed", "lib.tb_with_checks.Test failing check"),
     ("failed", "lib.tb_with_checks.Test non-stopping failing check"),