Thesis project topic: Design and implementation of scalable(N-point) FFT processor using VHDL for wireless applications

The project hosted on this site consists of the following:

1. Docs
2. simulation_results
3. synthesis_results
4. Deepak_Revanna_Thesis_Maturity_Test.pdf
5. Deepak_Revanna_Thesis_Presentation.ppt

*. The Docs folder contains the basic documentation about the FFT processor design details.

*. The simulation_results folder contains screen shots of simulation results of FFT computation for various N values.

*. The synthesis_results folder contains the screen shot of the results after synthesizing the design on an 
Altera stratix V FPGA.

*. The thesis maturity test("Deepak_Revanna_Thesis_Maturity_Test.pdf") is a plain text summary on the thesis topic 
presented to supervisor to test the maturity of understanding on the thesis project implemented.

*. The thesis presentation(Deepak_Revanna_Thesis_Presentation.ppt) contains the presentation slides on the thesis
project work presented before the thesis supervisor.