Hardware-acceleration-of-chess-engine

The purpose of this project is to give an insight in the process of making hardware which will accelerate the critical point of sowftware code. This process includes System Level design, RT methodology in hardware design and it's functional verification. In this project, I started with Tom's Kerrigan Simple Chess Engine Code(http://www.tckerrigan.com/Chess/TSCP/) and after time analysis done by CodeBlock's profiler, I realized that function attack and eval consumes the majority of processing time. The function attack just examine if some square is attacked by opponent or not, while eval evaluates the position and returns the integer that describes who is winning (it could be in range -10000 to 10000). I choose to implement function eval in hardware. The first step was to implement parallel model of eval function in SystemC. These files could be find in the directory SistemC_files. The next step was to implement that parallel model in VHDL and that is in VER/dut. The last step was to prove that designed model will work. This was implemented in SystemVerilog and the source code could be find in the folder VER/verif as well as run.do script. For the simulation I used QuestaSim.